EDA Design Page 121

his document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks of their respective owners. ============================================= HOW TO GET AND INSTALL A MODELSIM 10.0 RELEASE ============================================= *** IMPORTANT LICENSING CHANGE ****** IMPORTANT LICENSING CHANGE ****** IMPORTANT LICENSING CHANGE *** The 10.0 release uses the following licensing versions: FLEXnet...

Advanced Technology * Meets the needs of mid-sized to large electronics companies with complex PCB designs * Eliminates the burden of managing multiple tools, with its common database and user interface * Supports globally dispersed design teams with real-time collaboration * Maintains data integrity – from concept to manufacturing * Reduces design cycle time and manufacturing costs, while increasing productivity Integration As an Expedition Enterprise project evolves from concept to finished product, the database is always synchronized, notifying the engineer and designer of changes as they occur, eliminating unnecessary and costly design iterations. Expedition Enterprise is integrated with DMS™ (Data Management System) and CES (Constraint Editing System), providing a central infrastructure for component libraries, design data versioning and management, design...

Sigrity offers advanced software solutions for package physical design and for analyzing power integrity, signal integrity and EMC in chips, packages and printed circuit boards. Over 170 companies utilize Sigrity products as part of industry standard design flows from Sigrity, Cadence, Mentor Graphics, Altium, Zuken and AutoCAD.OptimizePI enables design teams to balance decoupling capacitor (decap) cost and performance for printed circuit boards (PCBs) and IC packages. Decap costs savings of 15% to 50% are typical. High performance is analytically assured for the power delivery system (PDS) at both a system and component level. OptimizePI is built on proven Sigrity hybrid electromagnetic circuit analysis technology in combination with our unique optimization engine to quickly pinpoint the best possible decap selections and...

PADS 9.3 is a completely separate installation from previous PADS releases and uses new installation methods to create an easier installation experience. Database and ASCII formats for Layout and Router designs have changed. The PADS library format has not changed. PADS Logic ASCII and database format are the same as PADS 9.x. The Installation path for PADS 9.3 is still C:MentorGraphics, but installs using a new folder to prevent overwriting an existing software installation. While PADS 9.3 installs the unique C:MentorGraphics9.3PADS folder and does not overwrite previous PADS installations, you should back up your existing PADS installation, designs and libraries prior to installing PADS 9.3.product:Mentor Graphics Pads 9.3 Lanaguage:english Platform:Winxp/Win7 Size:1.24 GB

This course addresses features specific to Incisive® mixed-language (VHDL, Verilog®, and SystemC®) event-driven digital simulation. The course treats these languages equivalently; students may do most labs in their choice of language. Learning Objectives Compiling, elaborating, linking, simulating, and debugging your design Optionally: * Simulating mixed-language designs * Annotating HDL design timing data * Integrating user C or C++ applications with an HDL design Agenda Day 1 1. Incisive simulation overview 2. Setting up the simulation environment 3. Compiling your design 4. Linking SystemC components 5. Elaborating your design 6. Simulating your design Day 2 1. Debugging with the textual interface 2. Debugging with the graphical interface 3. Employing simulator-related utilities If sufficient time: 1. Simulating mixed-language designs 2. Annotating SDF...

Ucamco release UCAM Version 9.1 – a PCB CAM automation breakthrough. With UCAM Version  9.1  any  experienced  PCB  CAM  engineer  can write  custom  automation scripts without being a trained programmer.  Gent, Belgium – December 24, 2010 – Ucamco have launched Visual HyperScript as the key feature  of  Ucam  Version  9.1,  the  second  major  UCAM  upgrade  for  2010.   Visual HyperScripting means that any experienced PCB CAM engineer can write custom automation scripts without being a trained programmer.  CAM  engineers  have  long  understood  that  the  key  to  the  fastest  and most  accurate  tool generation  throughput  is  customized  workflow  automation.   Until  now  this  has  needed specialist programming skills in third‐party languages like Java or C‐shell scripting.  As a result many CAM users have missed out on  the benefits of automation.  Alternatively,  they have found  themselves  limited  by  the  range  of  rather  simple  automation  options  available  or strait‐jacketed by inflexible automation programs. Ucamco’s  Visual  HyperScripting  provides  the  breakthrough  alternative.   Starting  from  a simple recording of a sequence of operations, any experienced CAM engineer can add new commands,  variables,  conditions  and  loops  to  generalize  the  recorded  script  into  an automated workflow.  The new  script  is  fully  integrated  into  the UCAM user  interface with clear  custom menus  and  dialog  boxes.   Visual  HyperScript  functionality  includes  intuitive tools and a powerful debugger  to make  the process  fast and accurate without  the need  to memorize  the  detailed  function  syntax.   Ucamco  report  that  field  tests  have  shown  that Visual HyperScripts can achieve time‐savings in excess of 95%. Karel Tavernier, Ucamco Managing Director,  comments:  “Our development goal has always been to deliver more productivity and higher efficiency to our users.  Visual HyperScripting offers this without the need for heavyweight programming.  Clear Help packages mean that existing  UCAM  users  can  benefit  from  Visual ...

CustomExplorer™ and Custom WaveView™ form a comprehensive transistor-level debugging environment for analog, mixed-signal and SoC designs. CustomExplorer provides a host of tools for navigating transistor-level designs and verifying simulation results. Download Datasheet IntroductionCustomExplorer is tightly integrated with Custom WaveView, enabling customizable waveform analysis. Custom WaveView provides powerful tools for displaying waveforms, performing calculations and making measurements (see Figure 1). Together, these tools aid designers in rapidly performing customized advanced analyses in a highly-productive design debugging and waveform analysis environment. CustomExplorer Design BrowsersThe Design Browsers allow quick access to the most complex hierarchy design data. After loading a netlist or simulation results, the user can probe the design’s hierarchy by expanding the Lint, File, Deck, Flat or Output View tabs. These...

NanoSim™ is the cornerstone of Synopsys’ comprehensive mixed-signal verification solution, Discovery AMS. NanoSim is an advanced transistor-level circuit simulation and analysis tool for analog, digital and mixed-signal design verification. It is a robust and easy to use solution, with very high simulation throughput and capacity for multi-million transistor SoC’s and accuracy for designs at 90 nanometer and below. Key Benefits * Provides high accuracy for designs at 90 nanometer and below * Simulation speeds up to orders of magnitude faster than SPICE * Capacity to simulate large memory and SoC designs, e.g. 512 Mb DRAM with 1 Billion elements * Provides flexibility to trade-off accuracy versus performance * Seamless integration with parasitic extraction tool, Star-RCXT for efficient post-layout simulation *...

Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies. Comprehensive SolutionThe Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage. Tessent™ Memory Test solutions provide the industry’s most advanced memory self-test and repair capabilities. Key features include comprehensive test and diagnostic capabilities to address the quality requirements of new process nodes and memory designs as well as...

Quartus® II software v10.1, the industry\’s number one software in performance and productivity for CPLD, FPGA, and HardCopy® ASIC designs, is available for download. The latest version introduces Qsys, a powerful new system-integration tool. Qsys, available in beta in Quartus II Subscription Edition software v10.1, saves time and effort in the FPGA design process by enabling faster system development and design reuse. Quartus II software v10.1 supports Altera’s new MAX® V CPLD family and the Arria® II GZ FPGA family, and provides expanded support for the Stratix® V FPGA family. The software continues to deliver new productivity features and enhancements, including an updated ModelSim®-Altera® Edition simulProduct:ALTERA QUARTUS II v10.1 Lanaguage:english Platform:Winxp/Win7 Size:4.36 GB