EDA Design Page 123

Quartus® II software version 10.0, the industry\’s #1 software in performance and productivity for CPLD, FPGA, and HardCopy® ASIC designs, is now available. Download Quartus II software today! •Quartus II v10.0 Subscription Edition Service Pack 1 is now available. •Quartus II v10.0 Web Edition Service Pack 1 is now available. Version 10.0 supports Altera\’s new high-performance, built-for-bandwidth devices: Stratix® V GX and GS FPGAs with integrated 12.5-Gbps transceivers. Stratix V GX FPGAs are optimized for high-performance, high-bandwidth applications. Stratix V GS FPGAs target high-performance, variable-precision digital signal processing (DSP) applications with the industry-first variable-precision DSP block. Future Quartus II software releases will also support partial reconfiguration, a Stratix V FPGA feature that reduces power, cost, and board space with more...

Cadence® PSpice® A/D is the de-facto industry-standard Spice-based simulator for system design. It simulates complex mixed-signal designs containing both analog and digital parts, and it supports a wide range of simulation models such as IGBTs, pulse width modulators, DACs, and ADCs. Its built-in mathematical functions and behavioral modeling techniques enable fast and accurate simulation of designs with efficient debugging. PSpice A/D also allows users to design and generate simulation models for transformers and DC inductors.Scalability options include PSpice Advanced Analysis capabilities and integration with MathWorks MATLAB Simulink for co-simulation. Advanced capabilities such as temperature and stress analysis, electro-mechanical simulation, worst-case analysis, Monte Carlo analysis, and curve-fit optimizers help engineers design high-performance circuits that are reliable and withstand parameter variation.Full integration...

Mentor Graphics Corporation (Nasdaq: MENT) today announced that STMicroelectronics has adopted the TestKompress® automatic test pattern generation (ATPG) product into its standard 65nm and 45nm design kits. The new test flow will enable high-quality scan-based production testing for applications such as automotive, cellular infrastructure, and imaging. “We’re benefiting from a very fruitful collaboration to incorporate Mentor Graphics’ Design-For-Test (DFT) technology into our advanced nanometer design flows starting at 65nm and below,” said Roberto Mattiuzzo, Digital Test Solutions manager of STMicroelectronics’ Technology R&D, Central CAD & Design Solutions. “With new failure mechanisms at advanced nodes, limitations on IC pins available for testing, and the need to employ better self-test in the field, the range of emerging testing requirements has significantly increased....

What\’s new in version 5?Version 5.10Internationalization * The manual and tutorial are now available in Chinese. * The EAGLE program texts have been translated to Hungarian (note that the texts provided by the Qt GUI library are not available in that language). * The EAGLE program texts have been translated to Chinese (note that the texts provided by the Qt GUI library are not available in that language). User Language * The new User Language functions neterror(), netget() and netpost() can be used to access remote sites on the Internet. * The User Language function t2string() now has an optional format parameter. * The User Language now provides functions for processing XML code (see \”Help/User Language/Builtins/Builtin Functions/XML Functions\”). * The...

Want a powerful, yet easy to use simulation environment? SynaptiCAD\’s simulation and debugging tools provide a standard interface for controlling all of your simulation tools. SynaptiCAD\’s timing diagram editors have the most extensive and accurate timing analysis features available in any timing diagram editor on the market including delay correlation, reconvergent fan-out, and clocks that model jitter and buffer delays. Three different levels of editing let you pick the best price and feature set for your application. Free yourself from the time-consuming process of manually writing Verilog, VHDL, and SystemC testbenches. Generate them graphically from timing diagrams.SynaptiCAD provides 3 levels of test bench generation to meet all your design needs. SynaptiCAD offers support for the latest test equipment and emulation...

Patch for EDA and PCB Cadence SPB / OrCAD 16.30 on September 1, 2010.This package fixes the problems were noticed in the following programs of package:for OrCADOrCAD_Capture_CISOrCAD_EE_DesignerOrCAD_FPGA_System_PlannerOrCAD_PCB_DesignerOrCAD_Signal_ExplorerPSpicefor Allegro SPBAPD_APSIAllegro_AMS_SimulatorAllegro_Design_Entry_CISAllegro_Design_Entry_HDLAllegro_Editor_RouterAllegro_PCB_LibrarianAllegro_PCB_RouterAllegro_PCB_SIAllegro_Physical_ViewerAllegro_System_ArchitectDigital_SiPFPGA_System_PlannerRF_SiP Package is applicable for updating any options for installing – Allegro SPB and (or) OrCADExtras. Information: When you integrate this service pack have the opportunity to create a backup for a rollback to previous version. To do this, check the box \”Backup Files\” window \”Installation Summary\”After installation, you must reapply the patcher (included in the distribution), because in the process of updating the previously patched files are replaced with new ones.This Hotfix, like all others for Allego SPB / OrCAD is cumulative, ie includes all previous updates. Year / Release Date:...

HDL Companion is the HDL designer\’s Swiss army knife. It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources. Complete design directories and design files are dragged into HDL Companion and a complete design overview is created in seconds, uncovering information regarding numerous aspects of the design. The GUI offers many ways to navigate through the design and explore the details you\’re looking for. The embedded fuzzy parsers accept any Verilog, VHDL or mixed HDL design code; even if the code is incomplete or contains errors. Syntactically correct HDL can also be linted to find problems not reported by the compilers. HDL Companion has a...

New Features Simulation throughput has been significantly improved. Many applications can expect throughput to double compared to previous versions. Implementation of Mentor Graphics License Scheme. Significant speed improvement on OpenMP multi-CPU support for the major processes in IE3D full-wave EM simulation engine. Implementation of automatic geometry connection for crossing 3D polygons. Integration of Physical Component Compiler Library (PCCL) for automatic geometry generation and simulations of parameterized vias, solder balls and wire bonds, etc. for both single-ended and differential structures. Implementation of 4-port differential via models into PCCL. Implementation of building wire bond structures using industrial standard profiles. Improvement of the User Defined Object in IE3DLibrary to provide users with more flexibility to build their own structures for EM tuning and...

The latest PADS release series delivers a host of changes that span all product areas and include significant productivity improvements and usability enhancements, in addition to extensive new product and design flow features. Highlights of improvements in the latest version of PADS 9.2 are listed below. Please review the PADS 9.1 Release Highlightson SupportNet for additional details. · PADS Archiver- The ability to archive your complete design project is now available from within PADS. This includes schematic designs (PADS Logic and DxDesigner projects), PCB designs and libraries, and additional user defined folders and files. If a PDF output license exists, PADS Archiver will generate a PDF file at the time of the archive. Output of this archive can be directed...

Includes additional software and GUI enhancements– Support for Stratix ® V devices (adding simulation support for DDR and high-speed serial interface (HSSI) functions and support for incremental compilation)– Final timing models for EP4SE820, EP2AGX190, EP2AGX260, and all Cyclone ® IV E 1.0-V devices– Final power models for all Cyclone III LS and Cyclone IV E devices Nios II Embedded Design Suite 10.0 Service Pack 1.0 – Generates warning message with workaround instructions for issues caused when using the NicheStack TCP / IP network stack with the μC / OS-II board support package The Altera Complete Design Suite contains the following software: – Quartus II Design Software including SOPC Builder and MegaCore IP Library– ModelSim-Altera VHDL and Verilog HDL Simulation Tool–...