EDA Design Page 127

The AWR Design EnvironmentTM (AWRDE) 2010 version includes the following new features, enhancements, and user interface changes. AWRDE documentation includes both PDF documents and CHM (Help) files. The PDF files are available for download from the AWR website and are also included on AWRDE CDs. The CHM files are available via the AWRDE Help menu. This document includes a brief description of each new or revised feature, and where applicable, a link to the location in the documentation that provides full feature details. The Help file links work automatically because the full set of documentation is installed with the software. To link from this document to the full feature details in PDF files, all of the PDF files must be...

VCS®, with multicore technology, delivers a 2x verification speed-up that helps users find design bugs early in the product development cycle. VCS multicore technology cuts down verification time by running the design, testbench, assertions, coverage and debug in parallel on machines with multiple cores. The combination of performance; advanced bug-finding technologies; Echo testbench coverage convergence for faster closure; a built-in debug and visualization environment; support for all popular design and verification languages including Verilog, VHDL, SystemVerilog, OpenVera, and SystemC™ and the proven VMM methodology help VCS users develop high-quality designs. The VCS solution’s advanced bug-finding technologies include full-featured Native Testbench (NTB), complete assertions and comprehensive code and functional coverage to find more design bugs faster and easier. Additionally, the VCS...

Saber is a multi-domain modeling and simulation environment that enables full-system virtual prototyping for applications in analog/power electronics, electric power generation/conversion/distribution and mechatronics. Decades of industry success and innovation have earned Saber a reputation as the solution of choice for design validation and optimization for automotive, aerospace and industrial systems. SaberRD: Desktop Environment for Power Electronic Design * Introduced in 2010 * Easy to use—Windows-based IDE * Novice accessibility—Expert flexibility * Proven technology * Demo/Student version Focus: Manage power electronic and mechatronic complexity by accelerating Robust Design via simulation * Automotive (mid-class car) — 50+ microprocessors, 100+ sensors, 30+ electrical subsystems * Aerospace (A380) — 530km of wires, 100,000 cable sections, 40,300 connectors * Solar — power electronics, control algorithms,...

MPro 2010.07 is a maintenance release for EMPro 2010. EMPro is a new design platform for analyzing the electromagnetic effects of RF and microwave components such as high-speed IC packages, antennas, on-chip and off-chip embedded passives and PCB interconnects. EMPro features the most modern design, simulation and analysis environment, highest capacity simulation technology and integration with the industry\’s leading RF and microwave circuit design environment, Advanced Design System (ADS) for fast and efficient RF and microwave circuit design.Whats new Platform Improvements * New Bondwire Geometry Component * ODB++ File Import * Several UI Enhancements (Boolean multiple objects, geometry transform shortcuts, etc.) * Transform functions: Scale, Translate, Rotate, Reflect, Shear for object manipulation * Windows 7 Support Finite-Difference Time-Domain (FDTD) Improvements...

High Level Synthesis High Level Synthesis reduces the manual effort required to create and completely verify synthesizable RTL code. Design size and complexity continue to push traditional RTL design and verification methodologies to their limits. Catapult C SynthesisFull-Chip High-Level Synthesis Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements.Traditional hardware design methods that require hand-written RTL development and debugging are too time-consuming and error prone for today’s complex designs. Catapult C empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult C generates production quality RTL. With...

VICTORY PROCESS3D PROCESS SIMULATOR VICTORY PROCESS is a general purpose 3D process simulator. VICTORY PROCESS includes a complete process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit. Proprietary models, as well as public domain research models, can be easily integrated into VICTORY PROCESS using the open modeling interface. Key Features * Sophisticated multi-particle and flux models for physical deposition and etching with substrate material redeposition * Extremely accurate and fast Monte Carlo implant simulation * Comprehensive set of 3D diffusion models: Fermi, three-stream, and five-stream * 3D physical oxidation simulation with stress analysis * Fast 3D structure prototyping capability enables the in-depth physical analysis of specific processing issues...

X-HDL 4 is the premier Verilog VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, \”hand tweaks\” of the translated code. X-HDL also contains specialized algorithms which are very effective in translating behavioral-level code to functionally equivalent target-language code. Key Features •Provides both GUI and command-line modes •Performs automatic hierarchical translations as well as file-at-time translations. •Translates structural, RTL and behavioral code •Preserves comments with placement nearly identical to the source •Consistent code formatting with user customizations ◦VHDL\’87 or VHDL\’93 syntax generation ◦Verilog-2001 syntax generation ◦Code alignment controls ◦Indentation controls ◦Line wrap controls •Supports component libraries •Smart overloaded subprogram handling •Intelligently determines if translated Verilog tasks/functions are local or global...

HyperLynx® Signal Integrity enables engineers to quickly and accurately analyze and eliminate signal integrity and EMI/EMC design problems early in the design cycle. HyperLynx Signal Integrity comes ready to use in virtually any PCB design flow and offers unprecedented time-to-results, improving productivity, reducing development and product costs, and increasing product performance.Mentor Graphics Corporation (NASDAQ:MENT) today announced it was honored by the International Engineering Consortium (IEC) with the annual DesignVision award in the System Modeling and Simulation Tool category for its HyperLynx® PI (Power Integrity) product. This solution delivers fast-time-to-accurate-results in the analysis of AC and DC behavior for printed circuit board (PCB) power distribution networks. The IEC announced the winners of the DesignVision Award at DesignCon on February 2, 2010....

Genesys 2010.05 was developed based on extensive inputs from a large Genesys user community. This release of Genesys went through the most thorough quality assurance (QA) and early access (EA) customer testing compared to all previous versions of Genesys. Not only does this release address multiple reliability and performance issues, it also adds breakthrough new capabilities such as X-parameters* to both the circuit and system simulators. These along with the simplified Genesys product structure and pricing put Genesys in the best price-performance of any RF/microwave simulation tool in the industry.Genesys 2010.05 now includes: * Breakthrough nonlinear X-parameter simulation and modeling technology to enable the most accurate and convenient RF nonlinear circuit and system designs. More information about X-parameters in Microwave...

Vera language was orginally developed in Sun Micro Systems for internal ASIC verification projects. Later VERA language with VERA compiler was marketed by System Science. System Science later sold Vera to Synopsys. Synopsys released closed Vera language as openVera, which was later implemented in VCS as NTB. Currently OpenVera is support is support by @hdl Simulator, and VCS Compiler. space.gif Later Synopsys donated parts of Vera language to Verilog to give Verilog unified design and Verification feature. This new language is called SystemVerilog.product:Synopsys Vera vD-2009.12 Lanaguage:english Platform:Linux Size:287 MB