EDA Design Page 138

Mentor Graphics AMS 2008.2 Linux Release. Questa ADMS gives designers a comprehensive environment for verifying complex analog/mixed-signal System-on-Chip designs. ADMS combines four high performance simulation engines in one efficient tool: Eldo® for general purpose analog simulations, Questa® for digital simulations, ADiT™ for fast transistor-level simulations and Eldo RF for modulated steady state simulation Analog and mixed-signal SoC designs combine analog and digital content more tightly than ever before. They increasingly depend on integrated analog blocks such as A to D and D to A converters, phase-locked loops, and adaptive filters. This increased level of integration puts tremendous pressure on designers. Traditional design tool flows force designers to develop analog and digital subsystems in isolation, delaying the integration of these components...

Mentor Graphics IC Flow 2008.2 Linux Release.It Supported RHEL 5 x86, as well as SLES 10 x86 are the newly supported operating systems. • VerificationIC Flow 2008.2 is compatible with Calibre 2008.3 and AMS 2008.1• EnhancementsNew file browser.New toolbar icons.Re-sizable dialog boxes.New command shell.Profiles.• Fixed defects and enhancementsFor a detailed list of the corrected defects and enhancements across the entire IC Flow product line in the 2008.2 release, refer to the Release notes for IC Flow in the manual: IC Flow Release Notes. Polygon editing functionality of ICgraph Basic, plus hierarchical, schematic-driven layout environment Dynamic connectivity display with cross-probing Ready-to-use, parameterized device generators dramatically improve efficiency while creating DRC-compliant layouts for digital and analog design Engineering Change Order (ECO) component...

Questa is Mentor Graphic’s Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.  Features product:Mentor Graphics QuestaSim 6.6 Win Lanaguage:english Platform:Winxp/Win7 Size:214MB

Mentor Graphics Corporation (Nasdaq: MENT) today announced the Questa™ Vanguard Program (QVP), a partnership with industry-leading companies to enhance the verification options for Questa users and build a strong and comprehensive SystemVerilog ecosystem. The Questa Vanguard Program extends Mentor Graphics breadth of verification technologies through partnerships with other industry-leading companies that provide verification related tools and methods, verification IP, conversion services, training and consulting. Through these technology alliances and strategic partnerships, Mentor Graphics leverages resources and technical expertise to deliver even greater value to Questa users, including strong product integration with other Mentor Graphics technologies (see news release \”Mentor Graphics Delivers the Next Generation of Functional Verification,\” May 8, 2006). \”Without adequate industry infrastructure, no new technologies or methodologies can...

CST proudly announces the upcoming release 2010 of its electromagnetic simulation software CST STUDIO SUITE™. With over 60 man years of research and development and over 3000 functional changes, CST STUDIO SUITE 2010 again sets the standard for electromagnetic simulation software. The focal points of 2010 development can be briefly summarized as implementing and integrating new solver technology, improving simulation performance and extending the applicability Product:CST Studio Suite 2010 win Lanaguage:english Platform:Winxp/Win7 Size:4.53G

EAGLE Product informationThe EAGLE Layout Editor is an easy to use, yet powerful tool for designing printed circuit boards (PCBs). The name EAGLE is an acronym, which stands for Easily Applicable Graphical Layout Editor The program consists of three main modules * Layout Editor * Schematic Editor * Autorouter which are embedded in a single user interface. Therefore there is no need for converting netlists between schematics and layouts. Program Features (Professional Edition)General * online Forward- and Back-Annotation * context sensitive help function * no hardware copy protection! * multiple windows for board, schematic and library * powerful User Language * integrated text editor * available for Windows, Linux and MacProduct:CadSoft Eagle 5.7 Lanaguage:english Platform:Winxp/Win7 Size:25MB

::::::English Description:::::: Synopsys Hspice 2009.09 Linux is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and comprehensive circuit simulator. Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield of their designs. As board and package speeds increase, designers need to employ increasingly accurate signal integrity analysis. <!– Key Benefits –> Accuracy Gold standard for accurate circuit simulation. Extensive model support of the most accurate and expansive set of...

Seismos, a transistor-level design product, is the first in the EDA market to analyze stress and well proximity effects in circuit-level designs in nanometer technologies. The Seismos model originates from TCAD simulations and is validated by silicon data, but the solution primarily aids circuit designers. Benefits Enable circuit designers to simulate and optimize the layout dependency of silicon stress effects on device characteristics and circuit performance Handle a wide range of design sizes from a few transistors to multimillions of transistors with high performance and memory efficiency Annotate the stress effects back to the SPICE netlist for circuit simulations Readily integrate into third-party design flows Provide a GUI mode for data visualization and real-time what-if analysis in a layout environment...

Synopsys Paramos 2009.03 SP2 is a process dependent Spice Model extraction tool specifically designed to extract process dependent Spice model parameters for detailed analysis of circuits with process variations. The graphical user interface (GUI) allows users to develop an extraction strategy, run extraction, and load Spice model card data into PCM Studio for visualization of extraction results. Key Features: Provides process-related SPICE parameters for detailed analysis of circuits with process variations; thereby closing the design for manufacturing gap Creates self-consistent process-dependent compact SPICE models with the actual process parameter variations as explicit variables Enables designers to comprehend the impact of manufacturing issues on design Allows designers to simulate the impact of process variability (statistical or systematic) on circuit performance for...

。 IAR Embedded Workbench for NEC 78K 4.62 FULL verion Release. IAR Embedded Workbench for 78K provides extensive device support and generates very compact and efficient code. Built-in plugins to various hardware debug systems and RTOSs are included in standard edition. Highlights in version 4.62 MISRA-C:2004 support Improved optimization IAR visualSTATE build integration Flash programming emulation and EEPROM emulation Text editor improvements Updated device support Key components Integrated development environment with project management tools and editor Highly optimizing 78K compiler supporting C and C++ Configuration files for all 78K0, 78K0S and 78K0R devices Emulator debugger support Run-time libraries Relocating 78K assembler Linker and librarian tools C-SPY debugger with 78K simulator and support for RTOS-aware debugging on hardware Example projects for 78K and code...