EDA Design Page 143

  Mentor Graphics SystemVision 5.4 is Mentor Graphics breakthrough System Modeling solution that allows system engineers and engineers from multiple disciplines to communicate, simulate, and optimize designs for first-pass success. SystemVision provides a virtual lab for design and analysis of analog, mixed signal, digital, and electro-mechanical designs. With SystemVision you can explore concepts, specify system functionality, investigate architectural partitions, and integrate implementation of electronics, sensors/actuators, controls, and embedded software, all in one virtual environment. The result is reduced development time, simplified HW/SW integration, and reduced manufacturing and warranty costs with SystemVision. Provides a virtual lab for creating and analyzing analog, digital, and mixed-signal systems Supports industry-standard languages: VHDL-AMS, SPICE, and C Allows design verification of hierarchical schematic and circuit elements...

Home : Products & Services : Design Tools : ISE Design Suite EvaluationISE Design Suite EvaluationDownload Evaluation*Buy ISE Design SuiteView Technical DemosRequest Evaluation DVD** Registration RequiredRelated InformationOperating System Support Evaluate all of the products in the ISE® Design Suite! Experience the most complete FPGA design solution for ultimate productivity, performance, cost reduction, and power management – FREE for 30 days! Xilinx makes it easy to evaluate the world-class FPGA, DSP and Embedded Processing system design tools in the ISE Design Suite. If you\’re looking at Xilinx for the first time or considering additional ISE Design Suite products for your FPGA design environment, a free 30-day evaluation license gets you started quickly. Download the ISE Design Suite and start your evaluation...

Electromagnetic Professional (EMPro) 2008 is Agilent EEsof EDA\’s new 3D electomagnetic simulation platform providing the industry\’s most modern, interactive, intuitive, and efficient environment. EMPro 2008 includes a new user interface, solid modeler, major simulators (32 & 64 bit), multithreading, cluster simulation, GPU hardware acceleration, and thermo- & bio-calculations such as Specific Absorption Rate (SAR) and Hearing Aid Compatibility (HAC). There are many examples of where Agilent\’s Advanced Design System (ADS) flow integration is critical to the success of a design, such as: * Packaging * Chip-to-board transitions like bond wires and solder bumps * Designing antennas with tunable matching circuits and multiple-input, multiple-output (MIMO) * Designing connectors and transitions * Low temperature co-fired ceramic (LTCC) circuits * Optimizing wireless designs...

Agilent RF Design Environment (RFDE) 2009 Linux provides access to the ADS circuit simulators directly from the Cadence Analog Design Environment (ADE). Note: RFDE is being replaced by Agilent\’s GoldenGate RFIC Design Software. RFDE 2009 is the last supported release. Agilent\’s GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE). ADS circuit simulators will continue to be accessible from ADE through the ADS Dynamic Link capability. Product:Agilent RF Design Environment (RFDE) 2009 Linux Lanaguage:english Platform:Winxp/Win7 Size:664MB

The Integrated Circuit Characterization & Analysis Program (IC-CAP) is the industry standard platform for DC and High Frequency measurement and modeling of semiconductor devices. IC-CAP 2009 continues to provide innovative modeling solutions by introducing two new turn-key modeling packages for extracting Corner Models for MOS devices and the BSIMSOI4 model for Silicon On Insulator (SOI) MOS devices. For the first time, IC-CAP 2009 adopts a new platform and user interface (UI) technology which dramatically improves the performance, responsiveness and provides a better look-and-feel of the product. In addition, this new release introduces several platform enhancements in the areas of PEL, graphics and instrument drivers. New Corner Modeling Extraction Package Unlike extracted models from measured data, which describe the behavior of...

The Integrated Circuit Characterization & Analysis Program (IC-CAP) is the industry standard platform for DC and High Frequency measurement and modeling of semiconductor devices. IC-CAP 2009 Update 1 continues to provide innovative modeling solutions by introducing several new model versions in MOS extraction packages as well as other enhancements and new features. The new model versions include HiSIM_HV 1.1.1, BSIM 4.6.2, and PSP 103.0. IC-CAP 2008 introduced running simulations in Spectre compatibilty mode with ADS, thus enhancing model generation and library maintainance efficiency, and IC-CAP 2009 Update 1 now introduces support for running ADS simulations in HSPICE compatibilty mode. Addition of a driver for the new B1505A Power Device Analyzer and Curve Tracer makes it possible to measure a new...

TimingDesigner is a flexible, interactive timing analysis and diagram tool. Its intuitive use of timing diagrams and patented spreadsheet technology allow users to model their unique timing challenges, analyze a range of conditions, obtain accurate results as well as monitor and manage timing margins throughout the design processCadence Allegro PCB Signal Integrity (SI) Interface TimingDesigner® 9.2 now provides a seamless integration with Cadence® Allegro® PCB SI to aide in more accurate timing analysis. Joint signal integrity and timing analysis is becoming increasingly important as design speeds grow, margins shrink, and project schedules shorten. This enhanced integration allows users to import simulated interconnect delays from Allegro PCB SI, enabling design teams to resolve timing issues early in the design process when...

Today, engineering teams in the electronics industry face unprecedented challenges in product development characterized by shorter design cycles, stringent cost constraints, new feature requirements, and smaller geometries. In order to help you accelerate through these challenges EMA has developed TimingDesigner® Design Kits: pre-assembled timing diagrams of common design components complete with all specified libraries for speed and voltage ratings. Design Kits give designers a time saving head-start for static timing analysis of their designs. They provide all documented timing protocols associated with commonly used design components such as SDRAM and DDR memory, as well as several common processors and FPGA libraries. Each Design Kit Component is parameterized where applicable so that configuration options affecting timing relationships are accurately represented, and...

With SpeedXP 8.0, Sigrity is introducing user-customizable workflows to enhance productivity for both new and experienced users.  Sigrity is providing seven default workflows for use with PowerSI and SPEED2000 covering topics such as a model extraction workflow, power ground noise simulation workflow and EMC/EMI simulation workflow.  Sigrity provided workflows can be tuned to adapt to individual / team preferences and users can also easily create their own workflows.  ENHANCEMENT SUMMARY Here is a quick feature summary.   Software releases are available for electronic download at Sigrity\’s Customer Sign-In area. Primary user contacts have account user name and password information.   Password retrieval is available at the SPDnet site. SpeedXP (8.0 Production Release) Overall SpeedXP capability:  Customizable workflows … for user defined...

Mentor Graphics IC implementation solution, Olympus-SoC™, delivers innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization. It also includes litho-driven routing that addresses optical proximity correction (OPC), resolution enhancement technology (RET), and critical area analysis (CAA) early in the design cycle, ensuring faster timing closure for complex process rules. Benefits of Olympus tools: Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization Reduce power consumption in clock trees with MCMM clock tree synthesis Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation Speed time-to-market with fewer design...