EDA Design Page 145

Remcom announces XFdtd 7.0 (XF7) training October 5-7, 2009 in Reston, Virginia, just outside of Washington DC. The training will teach current XFdtd users how to transition projects to XF7 and maximize productivity using the most advanced tools Remcom has to offer. In addition, anyone is welcome to attend to learn how XF7’s new features can speed design time in the development cycle. Whether currently using XFdtd or not, all attendees can expect to gain the following from the course: * Most efficient ways to use Remcom software and maximize productivity. * Overview of the wide array of problems Remcom’s products help to solve. * Coverage of new features and updates and how they benefit workflow. * Personalized consultations with...

The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.Product:Synopsys Synplify FPGA 2009.06 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:516MB

Synopsys Synplify FPGA 2009.06 Win As system complexities keep advancing, the complexity of programmable logic is following suit. High-density field programmable gate arrays (FPGAs) now contain millions of gates and operate at speeds in excess of 100 MHz. At this level of complexity, schedules, budgets and FPGA design tools all begin to feel the burden. Enter Synplify Pro® advanced FPGA synthesis solution. The Synplify Pro tool starts with all the features that made Synplify® software the industry\’s most popular and robust synthesis product, and moves beyond by providing additional capabilities. By using the Synplify Pro solution, you can push the performance of challenging and complex designs while remaining comfortably on or ahead of scheduleproduct:Synopsys Synplify FPGA 2009.06 SP1 Win Lanaguage:English...

Cadence Assura 4.10 Linux Physical Verification supports both interactive and batch operation modes with a single set of design rules. It uses hierarchical processing and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification incorporates advanced sub-65nm process parameter measurement, nanometer design rules for DFM, and process design rule checks. Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® custom design environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration...

FineSim Pro defines a new paradigm in full-chip circuit-level simulation, enabling the simulation of the most challenging analog/mixed-signal SoCs with SPICE accuracy and unprecedented performance. Combination of accuracy and performance in a single executable allows large, mixed-signal designs to be simulated with very accurate SPICE and fast-SPICE solving techniques. This provides complete control of speed- versus-accuracy tradeoffs throughout the entire design. Multi-CPU simulation enabled through Magma’s Native Parallel Technology TM delivers silicon-accurate results for very large complex systems (5M transistors and more) such as wireless systems on chip (SoCs) and full-chip memory designs. Electrically Exact Models TM (E2M) dramatically improve simulation performance by orders of magnitude with virtually no loss in accuracy compared to fast SPICE Typically, analog and digital...

ADS 2009 Update 1 is the 2nd of 4 quarterly releases in 2009 specifically targeted to double design productivity as measured in terms of reduction in simulation times, mouse clicks and activities needed to complete a design task. ADS 2009 Update 1 brings you the following exciting enhancements: 10x speedup in planar 3D electromagnetic simulation 10x speedup in non-linear circuit simulation Patent pending convolution technology that allows accurate signal integrity simulation with measured S-parameter data of high-speed interconnects New Simulation Models and Libraries Further improvement in graphical user interface The combined benefits of all the above translates to at least a doubling of your design productivity. 10x speedup in planar 3D electromagnetic simulation The 3D planar EM simulator, Momentum, in...

IntelliSuite 8.2 can Used by MEMS professionals worldwide for design, development and manufacturing of MEMS, IntelliSuite has firmly established itself as industry’s standard tool.  As such, IntelliSense provides MEMS companies and individual users with a complete living design environment. IntelliSuite is a tightly integrated design environment that will link your entire MEMS organization together. Built to scale from a point tool to an organization-wide tool, IntelliSuite unifies various engineering and manufacturing tasks into a single living design environment. Designed around collaboration, IntelliSuite allows the design and process teams collaborate on MEMS devices that can be prototyped and manufactured with fewer costly iterations. IntelliSuite starts the design process from fabrication machine settings, rather than device geometry — an approach that helps...

CoWare, Inc. has announced a major new release of its SystemC-based ConvergenSC SoC design tools to speed adoption of electronic system level (ESL) design methodologies by system designers and architects. The release combines new features that enable faster modeling and debug of IP models, platform subsystems, and SoC designs in SystemC, with an open environment that eases integration of internal tools and IP into the system-level flow. ConvergenSC now features a powerful SystemC integrated development and debug environment (IDE) based on Eclipse — the leading C++ development environment for embedded software — adding SystemC graphical debugging and a managed builds process to ConvergenSC\’s fast SystemC simulator and thread-aware debugging engine. Because Eclipse is open, users can easily integrate Eclipse plug-ins...

CoWare Processor Designer 2009.1 Programmable Accelerators for Platform-Driven ESL Design Integrated design environment for unified application specific processor, programmable accelerator design and software development tool generation Slashes application specific processor and programmable accelerator hardware design time by months Eliminates months of engineer-effort for software tool development Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation Software development environment enables application software development prior to silicon availability CoWare® Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time and engineer-month from the creation of application processor-specific software development tools. Processor Designer\’s high degree of automation enables design teams to focus on architecture exploration and application-specific processor development,...

CoWare Signal Processing Designer 2009.1 Implementing Algorithms for Platform-Driven ESL Design Highlights Industry\’s fastest, production proven signal processing simulator Fully supported on Windows and Linux 4000+ models with source code Unique standards reference libraries Fully integrated with MATLAB® and Catalytic MCS tools Fully integrated into CoWare platform-driven ESL design solution RTL cosimulation support for Cadence Incisive® and Mentor Modelsim® RTL code generation for Synopsys DesignCompiler® and Cadence Encounter® Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive® One-click analysis Powerful polymodeling capability State-of-the-art GUI for maximum productivity Scalable XML database Automated model migration from SPW designs OverviewCoWare® Signal Processing Designer (SPD) accelerates the design of complex, digital signal processing (DSP) systems. It is a C-based modeling and simulation environment that facilitates structured...