EDA Design Page 146

Denali PureSuite 3.2.062 Linux64 is the industry\’s most complete compliance suite for exercising designs and measuring compliance with the PCI Expresss specification, and ensuring interoperability with other PCI Express designs. Used with the PureSpec&trade verification IP product, PureSuite provides a comprehensive, automated solution for functional verification of PCI Express designsProduct:Denali PureSuite 3.2.062 Linux64 Lanaguage:English Platform:/Linux64 Size:5MB

Denali PureSuite 3.2 is the industry\’s most complete compliance suite for exercising designs and measuring compliance with the PCI Expresss specification, and ensuring interoperability with other PCI Express designs. Used with the PureSpec&trade verification IP product, PureSuite provides a comprehensive, automated solution for functional verification of PCI Express designsProduct:Denali PureSuite 3.2.062 Linux32 Lanaguage:English Platform:/Linux Size:137MB

Cadence  Incisive  Formal Verifier(IFV) allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits Speeds time to block design closure with early error detection, analysis, and debug Reduces risk of re-spin by finding bugs that other verification approaches miss Eases chip-level verification by delivering higher block-level verification quality Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies Supports all industry-standard assertion formats, including SystemVerilog Assertions (SVA),...

# Algorithms including LMS, normalized LMS, leaky LMS, fast block LMS, sign LMS, RLS, and QR-RLS# Filtered-X LMS and normalized filtered-X LMS algorithm for active noise/vibration control# Examples including adaptive noise/echo cancellation, adaptive system identification, and LPC# Simulation and LabVIEW FPGA code generation for fixed-point LMS adaptive filter# Support for Windows 2000/XP/Vista/7 and LabVIEW Real-Time The NI LabVIEW Adaptive Filter Toolkit provides tools for designing, analyzing, and simulating adaptive filters, including both floating- and fixed-point. You can use these tools to create adaptive filters with various algorithms, such as least-mean-square (LMS) and recursive-least-square (RLS), as well as their variants. You can apply the adaptive filters you create to different applications, such as adaptive noise cancellation, adaptive echo cancellation, and system...

Well-maintained and consistent libraries are the keys to efficient design work in Expedition PCB®. The \”Library Manager™ for DxDesigner® to Expedition® PCB Flow\” course will give you the skills necessary to create, protect, add to and change the different data types in your Central Library. The lecture modules discuss the Central Library philosophy as well as how to use the Library Manager tools and how to best interface library objects into your design process. Hands-on lab exercises reinforce the lecture topics as you create a small library of symbols, parts, and cells from scratch under the guidance of our industry expert instructors.You will learn how to * Start a new Central Library and copy elements between libraries * Create partitions...

Well-maintained and consistent libraries are the keys to efficient design work in Expedition PCB®. The \”Library Manager™ for DxDesigner® to Expedition® PCB Flow\” course will give you the skills necessary to create, protect, add to and change the different data types in your Central Library. The lecture modules discuss the Central Library philosophy as well as how to use the Library Manager tools and how to best interface library objects into your design process. Hands-on lab exercises reinforce the lecture topics as you create a small library of symbols, parts, and cells from scratch under the guidance of our industry expert instructors.You will learn how to * Start a new Central Library and copy elements between libraries * Create partitions...

Agilent RF Design Environment (RFDE) provides access to the ADS circuit simulators directly from the Cadence Analog Design Environment (ADE). Note: RFDE is being replaced by Agilent\’s GoldenGate RFIC Design Software. RFDE 2009 is the last supported release. Agilent\’s GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE). ADS circuit simulators will continue to be accessible from ADE through the ADS Dynamic Link capability.Product:Agilent RF Design Environment (RFDE) 2008 Update2 Linux Lanaguage:english Platform:Winxp/Win7 Size:572MB

Agilent RF Design Environment (RFDE) provides access to the ADS circuit simulators directly from the Cadence Analog Design Environment (ADE). Note: RFDE is being replaced by Agilent\’s GoldenGate RFIC Design Software. RFDE 2009 is the last supported release. Agilent\’s GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE). ADS circuit simulators will continue to be accessible from ADE through the ADS Dynamic Link capability.Product:Agilent RF Design Environment (RFDE) 2008 Update2 Linux Lanaguage:english Platform:Winxp/Win7 Size:572MB

Integrated development environment and optimizing C/EC++ compiler for dsPIC/PIC24IAR Embedded Workbench with its C and EC++ compiler provides full support, including DSP support, for all devices in dsPIC and PIC24 families and has tight integration with MPLAB from Microchip. Highlights in version 1.40Download free 30-day evaluation edition * Support for the MPLAB REAL ICE in C-SPY * New Integrated Development Environment * Stack plugin Please read Product news for more details. Key components * Integrated development environment with project management tools and editor * Highly optimizing C and Embedded C++ compiler for dsPIC and PIC24 * Run-time libraries * Relocating dsPIC/PIC24 assembler * Linker and librarian tools * C-SPY® debugger with dsPIC/PIC24 simulator and support for RTOS-aware debugging on hardware...

Synopsys System Studio tool 2009.03 SP1 Linux Release! System Studio is a high performance, model-based algorithm design and analysis tool, combining unmatched simulation performance with high modeling efficiency plus the industry\’s best integration into the chip implementation design and verification flows. Leading wireless companies rely on Synopsys’ System Studio to address their system-level design needs — in fact, more than half of all mobile phones worldwide rely on algorithms designed with System Studio!product:Synopsys System Studio tool 2009.03 SP1 Linux Lanaguage:English Platform:/Linux Size:469MB