EDA Design Page 150

Tanner Tools 14 provides electronic design automation (EDA) software used by companies in a wide variety of industries. Its solutions enable designers to move rapidly from concept to silicon by enabling the design, layout, and verification of analog/mixed-signal ICs, ASICs, and MEMS. Tanner EDA solutions offer designers the perfect combination of price and performance to meet any design challenge. The company\’s solutions include tools for: Schematic Capture: S-Edit Simulation: T-Spice, W-Edit Physical Layout: L-Edit Verification: HiPer Verify, L-Edit Standard DRC, L-Edit LVS and more Parasitic Layout Extraction: HiPer PX, 2D and 3D parasitic layout extraction These scalable solutions have a range of applications in the biomedical, consumer electronics, next-generation wireless, imaging, power management, and RF market segments. Product:Tanner Tools 14...

EMIStream is the solution that can suppress undesirable electromagnetic radiation or electromagnetic interference (EMI) generated from printed circuit boards. HOW DOES EMIStream WORK?At the placement design stage (pre-routing), EMIStream examines optimal placement locations for parts by using imaginary routing and verifies the effects of the proposed EMI solution. EMIStream also can suppress resonance which occurs between the power and ground (GND) planes by analyzing the resonance which occurs by changing the locations of capacitors. By eliminating the causes of unnecessary electromagnetic radiation from the initial design stage, EMIStream substantially reduces the time and costs needed for revision after the prototype is developed and enables rapid time-to-market.Product:EMIStream 3.1 Lanaguage:english Platform:Winxp/Win7 Size:10MB

WILSONVILLE, OR–(Marketwire – May 27, 2010) – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Calibre® nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits. This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations. The iLVS specification, which was co-developed by Mentor and TSMC, separates the rule definition syntax from underlying rule implementations. This allows Mentor to optimize the underlying implementation, reducing the need for users to tune the general rule specifications themselves. Moreover, by using iLVS in conjunction with the Calibre nmLVS Advanced Device Properties (ADP) facility, the Calibre...

entor Graphics Corporation (Nasdaq: MENT), the market leader in printed circuit board design (PCB) solutions, today announced the availability of the next generation of PADS® flow with the introduction of PADS2007. This newest release offers layout designers and engineers the ability to implement RF and microwave circuitry using highly automated functionality, perform design for fabrication (DFF) checking early in the design process, and optimize performance with advanced high-speed analysis/verification functionality, thus significantly improving their productivity and design quality. “Mentor Graphics continues to invest in the future of PADS by strengthening the capabilities of designers to integrate RF circuitry design, high-speed net analysis and routing, and DFF into the PADS design flow,” said Dan Boncella, director of marketing, System Design Division,...

SystemCrafter SC 3.0 is a SystemC synthesis tool for Xilinx FPGAs. Breakthrough price of $3000 brings SystemC synthesis within reach of everyone. Use SystemC, the industry-standard addition to C++ for describing hardware. Design, debug and simulate hardware and systems using the SystemCrafter GUI or your existing C++ development environment. Develop hardware and software in the same framework. Descriptions are fast to write, fast to simulate, maintainable and readable, improving time to market. Eliminates time-consuming and error-prone manual translation of SystemC to HDLs. SystemCrafter SC 3.0 generates RTL VHDL or Verilog for downstream synthesis to Xilinx FPGAs, and closes the verification gap by writing a structural SystemC output for simulation. SystemCrafter SC is fully compatible with major C++ compilers, such as...

Recent collaboration between UMC and Synopsys has resulted in a complete RTL-to-GDSII reference design flow, which now includes critical design for manufacturing features for UMC抯 90nm process. Suzanna Chang, Senior Director of Marketing for UMC, and Paul Lai, Group Manager of Strategic Alliances, Synopsys, explain how the use of this flow can help designers reduce design risk and speed time to results. UMC\’s Design for Manufacturing (DFM) efforts supplement the basic design work that is performed to support customers. This helps increase the chances of first time silicon success, which is critical in reducing time to market and overall costs at technologies of 90nm and below. Improved DFM solutions help customers realize enhanced yields, faster turnaround times, and reduced risk...

Xtensa Xplorer is the only SOC design environment that integrates software development, processor optimization and multiple-processor system-on-chip (SOC) architecture tools into one common platform. You can access powerful design automation tools that ease the creation of Xtensa processor-based SOC hardware and software.www.inshares.com The Xtensa Xplorer IDE serves as the cockpit for the entire design process and provides all the tools necessary for processor and TIE development, software development, and modeling and simulation. Tensilica’s Xtensa Xplorer GUI serves as the cockpit for the entire designexperience. From Xtensa Xplorer, you can profile your application code, identify “hot spots” that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, you can...

Synopsys’ Star-RCXT™ is the electronic design automation (EDA) industry’s gold standard forparasitic extraction. It provides a single solution for ASIC, system-on-chip (SoC), digital custom,memory and analog designs. Trusted by over 250 semiconductor companies and proven in thousandsof production designs, Star-RCXT delivers fast and sub-femtofarad accurate technology. The Star-RCXT solution offers advanced capabilities needed for sub-65-nanometer (nm) designs, includingvariation-aware parasitic extraction, chemical-mechanical polishing (CMP) based and litho-awareextraction, inductance extraction and analog mixed signal design flow. Its seamless integration withindustry leading physical verification, circuit simulation, timing, signal integrity, power, reliabilityand RTL2GDSII flows enables unmatched ease-of-use, increased productivity and reduced time-to-market. Star-RCXT is used by leading foundries to solve process modeling challenges at 65-nmand 45-nm.product:Synopsys Star-RCXT 2008.12 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:138MB

Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time.product:Synopsys Formality 2008.09 SP4 Linux Lanaguage:english Platform:Winxp/Win7 Size:55MB

::::::English Description:::::: The Formality® Equivalence Checker uses formal techniques to prove or disprove equivalence between two versions of the same design. Equivalence checking is a type of static analysis that verifies large designs both quickly and completely without the use of test vectors. The high performance and reduced risk of static analysis has led to the rapid adoption of equivalence checking within leading verification flows, making it a must for all competitive design processes.  Key Benefits共享软件资源网 Exhaustive verification, without test vectors, in a fraction of the time consumed by traditional dynamic techniques Proves functional correctness of register retiming, complex datapath, ECO, and low power implementations–from within a single product Reduces manual setup with verified automated setup guidance Verifies full-custom and...