EDA Design Page 151

This morning Synopsys publicly announced the long-rumored–and demonstrated in the private rooms at DAC–Orion project: a custom and cell-based analog-mixed-signal (AMS) design environment aimed at breaking the dominance of Cadence\’s Virtuoso platform. By targeting what they see as changes in the requirements placed on AMS designers since the architecting of Virtuoso–while replicating much of the look and feel of that market-leading platform–Synopsys apparently hopes to position Orion, now formally known as Custom Designer, as the next-generation mainstream AMS design environment. And these requirements changes have been profound. The most mundane, but the most disabling change in the AMS landscape has been simply the enormous growth in the size of designs. This has made capacity, and especially simulation capacity, a critical...

This morning Synopsys publicly announced the long-rumored–and demonstrated in the private rooms at DAC–Orion project: a custom and cell-based analog-mixed-signal (AMS) design environment aimed at breaking the dominance of Cadence\’s Virtuoso platform. By targeting what they see as changes in the requirements placed on AMS designers since the architecting of Virtuoso–while replicating much of the look and feel of that market-leading platform–Synopsys apparently hopes to position Orion, now formally known as Custom Designer, as the next-generation mainstream AMS design environment. And these requirements changes have been profound. The most mundane, but the most disabling change in the AMS landscape has been simply the enormous growth in the size of designs. This has made capacity, and especially simulation capacity, a critical...

PROTEUS 7.5 SP3 新增功能ISIS 部分：全新的用户界面： 鼠标移动到对象上方时，会有可视化提示。 不同的鼠标指针类型显示该对象将进行的不同操作。 高效率非模态选择、布线。 便利的鼠标运用——左键选取、放置，右键提示菜单。 更加便捷的块操作方式，可调整选取区域及可定义的拾取点。 改进的鼠标滚轮的摇摆及缩放工具，使得设计导航操作更加便捷。全新的设计浏览器： 提供一个全局电子视图，包括设计部件列表及网络列表。 部件列表视图以页面、部件和引脚显示整个设计。 网络表视图以页面、部件和引脚显示整个设计。 层次化设计，可深入到元件引脚信息。 在原理图及PCB 中支持页面、部件、网络层次的交叉探测。设计浏览器：设计浏览器是一种PROTEUS 特有的工具，它提供WINDOWS 风格的用户界面，用户可以利用它就设计的不同层次进行导航和检查。它不仅可以查询一个原理图现有状态，以此来判断元件连接、封装的正误。同样可以导航原理图及PCB 间任何感兴趣的条目（通过对PCB 封装的交叉探测或者一个封装网络信息进行）。这个设计浏览器可以通过下列两种方式现实原理图信息：部件列表视图：这个视图提供一个原理图的硬件表述，包括层次化、组件及组件引脚等信息。例如：设计含有多个原理图，使用者可以快捷的进行切换并逐层分析，从元件列表到显示元件引脚的列表。网络网络表视图：这个视图提供一个原理图连接关系的表示，包含原理图中的所有网络以及连接到选定网络的引脚信息。使用者可以使用设计浏览器直接导航至原理图或相应ARES LAYOUT 中自己感兴趣的地方。这些都是非常简单易于操作的，在指定项目上点击鼠标右键，选择合适的导航选项获取需要的结果。ARES PCB 设计：全新的用户界面： 鼠标移动到对象上方时，会有可视化提示。 不同的鼠标指针类型显示该对象将进行的不同操作。 可通过新的选择滤除器进行非模态选择并对可选对象进行即时配置。 便利的鼠标运用——左键选取、放置，右键提示菜单。 更加便捷的块操作方式，可调整选取区域及可定义拾取点。 改进的鼠标滚轮的摇摆及缩放工具，使得设计导航操作更加便捷。全新的3D 可视化引擎： 提供当前布板的3D 可视图形。 简便直观的鼠标导航操作。 简单的命令集与实时预览使用户易于应用3D 信息。 单命令实现3D 数据从库集合到现有设计的应用。 更加便捷的块操作方式，可调整选取区域及可定义拾取点。 可通过标准的.3ds 文件格式导入定制的3D 模型。3D 可视化工具：3D 可视化工具（3D VIEWER）是ARES 提供的一种PCB 成板预览工具。这对于进行PCB LAYOUT 是非常有用的。3D3D 预览含有一个非常强大的导航系统，可以很便捷的通过鼠标来进行操作。ARES 库支持3D 封装预览，并提供完整的定制封装资料。仿真（ProSPICE/VSM）：全新的仿真顾问： 结构化的仿真信息显示。 根据问题严重性的彩色信息提示。 信息包含源信息与时间信息。 用户可根据需要采用交叉探测返回源器件或网络。 带文本帮助的错误信息有助于解决仿真故障。全新的仿真诊断系统： 提供对仿真运行跟踪模式的完全控制。 关于系统信息、CPU 及外设的详尽诊断信息。 可以在警告、每个分组的跟踪或调试时使能诊断。 强大的调试帮助包括仿真行为的完整文本报告。增强的工业级仪器： 全新的示波器，包括光标、打印、单次扫描等功能。 全新的逻辑分析仪，包括光标、打印、单次扫描等功能。新增的处理器模型： Proteus VSM for PIC24。 Proteus VSM for ARM7 扩充了 LPC2131/2/4/6/8 and LPC2101/2/3。 Proteus VSM for PIC18 扩充了 PIC18F24J10/44J10/25J10/45J10。 Proteus VSM for PIC16 扩充了 PIC16F873A/874A/876A/877A 。新增的高级外设模型： 新增ENC28J60 和 RTL8019AS 以太网控制器模型。 含SPI EPROMS, ADC/DAC 等器件的增强的嵌入式外设库。 ::::::English Description::::::Product:Proteus Professional 7.5 SP3 Lanaguage:English Platform:/WinNT/2000/XP Size:64MB

Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus Process is a new-generation process simulator for addressing the challenges found in current and future process technologies. Equipped with a set of advanced process models, which include default parameters calibrated with data from equipment vendors, Sentaurus Process provides a predictive framework for simulating a broad range of technologies from nanoscale CMOS to large-scale high-voltage power devices. Sentaurus Process is part of the comprehensive Synopsys suite of core TCAD products for multidimensional process, device, and system...

AUCOPLAN integrates data and documents from electrical and electro-mechanical engineering, automation technology, and process engineering planning.AUCOPLAN is characterized by maximum flexibility and adaptability to special labeling instructions, engineering processes and documentation regulations.AUCOPLAN can be obtained internationally through AUCOTEC\’s Global Partner Network, conforms to internationalstandards and is available in various language versions. AUCOPLAN supports current trends and technologies such as multi-user and client/server environments, database-driven engineering and object oriented modular design. AUCOPLAN has found its place among the market leaders of integrated I&E planning systems and has numerous references from its worldwide network, which includes leading companies of industrial sectors using DIN or ISA standard documentationProduct:Aucotec ELCAD Aucoplan 7.5 Lanaguage:english Platform:Winxp/Win7 Size:257MB

Foundry giant Taiwan Semiconductor Manufacturing Co. said today that it was engaging intellectual property player Virage Logic Corp. to develop libraries in support of early users of TSMC\’s 65nm technology. The agreement provides chip designers with memory compilers for SoC designs, the foundry said. It announced plans for 65nm production earlier this year. At every new technology node, the amount of chip space taken by on-chip memory increases dramatically, Edward Wan, senior director of design service marketing for TSMC, said in a statement. At the 65nm node, on-chip memory may occupy more space than logic or any other IP and therefore it\’s important for our customers to get early access to advanced memory compilers. Virage Logic is both a provider...

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains. In fact, it addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques. An RTL or gate-level simulation of a design (that has multiple clock domains) does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process. The 0-In CDC verification solution rectifies this problem. The 0-In CDC verification solution sets the industry benchmark by providing the three essential elements for a...

  Mentor Graphics Design for Test v8 2009.1 Linux 确保设计能于制造后正确工作 DFT工具为设计的可测性增加了设计电路（RTL或者gate level） DFT工具为投入生产的设计生成测试组来检测其缺陷 基于DFT结果进行失效分析 product:Mentor Graphics Design for Test v8 2009.1 Linux Lanaguage:English Platform:/Linux Size:278MB

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...