EDA Design Page 153

Mentor Graphics Design Capture-Expedition Flow 2007.5 Win32 为完成高密度PCB 与薄膜MCM 的布局、分析与生产提供最具生产力的工具。为最大限度地提高生产能力，用户可迅速、简便地访问所有基本设计工具。在能快速完成100%布线的编辑环境中，即使设定了最苛刻的规则，Expedition PCB Pinnacle 也可保证用户在板上集成所有器件。Expedition PCB Pinnacle 不断被证明是独一无二的最佳工具。得到用户所需的竞争能力、快速上市时间及最大的生产能力Expedition PCB 的界面可完全由用户定义，避免了由于工具的繁琐而给生产带来的阻碍。用户可根据自己的需要以图形方式对Expedition PCB 的下拉菜单、图标工具栏、功能键及快捷键进行定义。从设计环境中去除不常用的命令，可获得最高的生产效率。工具间通讯能力保证设计计划按正确方向发展Expedition PCB 通过ITC(工具间通讯)与Design Capture 紧密集成。ITC 保证Design Capture 与Expedition PCB 数据库总保持同步，并在任何环境中发生修改时通知系统工程师或PCB 设计者。随着项目由概念转向最终产品，原理图与PCB 不匹配的危险被降至最低，同时也避免了不必要的、价格昂贵的重复设计。有了ITC，所有设计人员均使用当前数据进行工作，从而避免了推迟上市时间及PCB 生产与原始设计脱节等问题。良好的工具间集成可使多个设计人员同时对电路的不同部分进行定义、仿真及设计，从而提高了设计的可靠性与生产效率。布局/布线—- 目前世界上功能最强的布线器在进行器件布局、布线时，Mentor Graphics 的高级编辑器无疑是最佳环境。交互与自动模式均采用最新技术实现可生产的高质量印刷电路版设计。信号规则和限制条件从电路的设计输入阶段传递过来，保证首次即正确布线。为在投产前完成修改，只需打开自动布线器的动态推挤选项。采用这一全自动、高级的布局、布线工具，用户将获得无以伦比的能力，以最高的效率完成设计工作。享有盛誉的交互、批处理自动布线器由于采用基于形状的无网格布线技术，Expedition PCB 提供了更高的性能与布通率，为得到较高的效益，用户可根据生产需要制定设计规则。片刻完成“最后一分钟修改”   Mentor Graphics Design Capture-Expedition Flow 2007.5 Win32 is a state-of-the-art front-end design package. Driving a full suite of digital and analog simulation and design tools, Design Capture enables you to rapidly and easily realize your design concepts, bringing them to life faster, and more accurately and profitably than ever before. Design Capture gives you the freedom to use traditional schematic-based entry with methods that are already familiar and comfortable to you. During creation, designs may be partitioned into various functional blocks and...

HyperLynx® Signal Integrity enables engineers to quickly and accurately analyze and eliminate signal integrity and EMI/EMC design problems early in the design cycle. HyperLynx Signal Integrity comes ready to use in virtually any PCB design flow and offers unprecedented time-to-results, improving productivity, reducing development and product costs, and increasing product performance.Signal integrity (SI) analysis is an essential part of modern electronic design. Increasingly fast edge rates in today’s integrated circuits (ICs) cause detrimental high-speed effects, even in PCB designs running at low operating frequencies. As driver ICs switch faster, a growing volume of boards suffer from signal degradation, including over/undershoot, ringing, glitching, crosstalk, and timing problems. When degradation becomes serious enough, the logic on a board can fail. Hardware engineers,...

::::::English Description:::::: Sonnet Suite Release 12 3D Planar High-Frequency Electromagnetic Software Sonnet s suites of high-frequency electromagnetic (EM) Software are aimed at today s demanding design challenges involving predominantly planar (3D planar) circuits and antennas. Predominantly planar circuits include microstrip, stripline, coplanar waveguide, PCB (single and multiple layers) and combinations with vias, vertical metal sheets (z-directed strips), and any number of layers of metal traces embedded in stratified dielectric material. The Sonnet Suites develop precise RF models (S-, Y-, Z-parameters or extracted SPICE model) for planar circuits and antennas.  The software requires a physical description of your circuit (arbitrary layout and material properties for metal and dielectrics), and employs a rigorous Method-of-Moments EM analysis based on Maxwell s equations that...

3D EM Simulation XFdtd® is a 3D EM simulation software package that provides engineers with powerful and innovative tools for modeling and EM simulation. It was designed to be simple and easy to use, but with the power to handle the toughest simulations that engineers face today.XFdtd Release 7 XF7 is the market\’s most modern 3D electromagnetic simulation software for FDTD-based modeling and simulation. XF7 simplifies workflow with an overall focus on the iterative nature of the design process. Remcom continues to invest in features and enhancements that improve the power, speed, and usability that have always been the core strengths of our software. Unique capabilities of XF7 include: * XACT Accurate Cell Technology resolves the most intricate designs with...

！ Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. But these advanced low-power design methods also complicate the verification task, introducing risk during synthesis and physical implementation. Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Cadence® Encounter® Conformal® Low Power enables designers to verify and debug multimillion-gate designs optimized for low power, without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use. Features/Benefits Minimizes silicon re-spin risk by providing complete verification coverage Detects low-power implementation errors early in the design cycle Verifies multimillion-gate designs much faster than traditional gate-level simulation Closes...

TINA v8 and TINA Design Suite v8 are upgrades of the earlier programs, TINA for Windows, TINA Plus for Windows and TINA PRO 5.0 5.5, 6.0 and 7.0 already in wide use throughout the world. New features of TINA v8 and TINA Design Suite v8 TINA v8 • Vista style installation and folder scheme• Behavioral building blocks, nonlinear controlled sources• Powerful Spice-VHDL co-simulation including MCUs• Finite State Machine (FSM) editor with VHDL generation• Flowchart editor and debugger for controlling MCUs (in v8.0 for PIC MCUs only)• Any number of MCUs in one circuit• Extended MCU catalog including PIC18, CAN and more• Execution time measurement and statistics for Transient Analysis• Hyperlinks can be added to schematics and to the diagram window•...

Encounter Timing System Accelerate design closure and signoff with a single view of timingEncounter Timing System serves both front-end logic designers looking for high-quality, high-throughput timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff. With Cadence® Encounter® Timing System, designers benefit from a consistent, integrated, multi-CPU enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence. Encounter Timing System helps designers analyze and debug multimillion-gate designs with significant gains in productivity. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and...

The Cadence® rF SiP Methodology Kit accelerates the application of eDAtechnologies to system-in-package (SiP) designs for radio Frequency(rF) and wireless applications. it provides methodologies that maximizedesign productivity and predictability for customers leveraging theadvantages of SiP technology. An integrated set of products built aroundproven methodologies enables complete front-to-back SiP design andimplementation. All this is demonstrated on a segment representativedesign, resulting in reduced time to new products, increased functionaldensities, and higher system performance.CADENCE SIP DESIGN TECHNOLOGYCADENCE RF SIP METHODOLOGY KITManufacturers of high-performance consumer electronics areThe Cadence rF SiP Methodology Kit leverages new SiPturning to SiP design because it can provide a number oftechnologies and verified advanced methodologies for rF SiPadvantages over just SoC. in addition to reduced cost, lowerdesign. it enables wireless...

WASP-NET （WAveguide Synthesis Program for waveguide NETworks）6.7是德国MIG公司的产品，MIG公司成立于1993年，自成立之日起，便与世界领导厂商建立起合作关系，在空间领域、无线通信和微波市场取得了巨大的成功，赢得了国际范围内的广泛认可。MIG公司由德国不来梅大学著名的Fritz Arndt教授创建。25年多来，Arndt和他的同事一直致力于波导类器件和天线的快速设计和仿真算法研究，在模式匹配和有限元、矩量法、差分方法的混合方面一直保持着世界领先的水平，Arndt教授一人已经发表了超过200篇的国际学术论文。WASP-NET在业内第一个采用了快速MM（模式匹配法）与FE（有限元）/ MoM （矩量法）/ FD （有限差分）4种方法的混合求解技术，即保证了求解精度和灵活性，又大大提高了效率。在WASP-NET中，一个典型的波导滤波器从设计、仿真到优化，在普通的PC机上仅仅需要不到10分钟的时间；一个带功分馈电网络的248槽波导缝隙行波阵列，在512MB内存的笔记本电脑上分析一个频点仅需60秒钟。 Product:MIG WASP-NET 6.7 Lanaguage:English Platform:/win2000/winxp Size:325MB

GraphiCode announces the release of StackupBuilder, a new product that allows modeling of PCB builds in a graphic environment. This provides valuable information about the physical build of the board allowing for reduced material costs. StackupBuilder uses the same data structure as all current GraphiCode products allowing compatibility between products. StackupBuilder is a combination of client-based application with a web service providing additional crucial material information via a user controlled database and license security. This allows StackupBuilder to run without a security dongle. When a stackup has been created within StackupBuilder it can be saved in the GWK and GraphiCode has allowed GC-Prevue to be able to view this stackup information along with the Gerber information in order to allow...