EDA Design Page 155

这是一款意大利产出的电磁三维软件EM3DS (Electromagnetic 3D Solver)。它是新奇、全功能、频率领域充足波浪仿真工具，有效地完成类似平面结构的化验。关于复杂的底层的专门平面结构，限定导电品的厚度和绝缘体的不连续性被视为防止危险的发生。因此，提供全面三维工具应用于EM3DS。 EM3DS使用 method-of-moments (MoM)技术，提供理想的2.5 与 3D仿真能力。使设计者可以对微系统电磁效果进行快速的、可定制的模拟。这个仿真工具可以作为CoventorWare的补充，用于RF，microware，及其他MEMS 器件。同时，EM3DS也可以作为一独立的产品来使用。相对于传统的有限元法，method-of-moments适合于高纵横比的结构（最大特征尺寸与最小特征尺寸比例很大）。method-of-moments能在纵横比是一重要考虑因素的地方，比如平板结构，进行更快的2.5 与 3D 仿真（比传统工具快50%-300%）。 鼠标轻轻一点，Coventor公司的EM3DS就可以由非常详尽的3D仿真转换到2.5D仿真。EM3DS非常适合处理整合了绝缘层、薄金属、以及绝缘夹杂物等等的复杂结构。 软件具有前后处理能力，可以进行linear circuit analysis, network parameters, Smith charts, S-parameters and SPICE extractions。能够输入的文件格式包括GDSII, AutoCAD DXF 和 BMP。 EM3DS (Electromagnetic 3D Solver) is a novel, full-featured, frequency-domain full-wave simulaton tool tailored to efficiently accomplish the analysis of quasi-planar structures – specifically planar structures over complex substrates, where the finite conductors’ thickness and the dielectric discontinuities are accounted for with no compromise – thus, rendering EM3DS a full 3D tool. Version 2008 is a new great step forward for EM3DS, now featuring: · Magnetic walls]: top and bottom cover may be magnetic wall (namely tangential H vanishing); by the same token two of the 4 side walls may be magnetic ·...

芯片设计解决方案供应公司微捷码(Magma)设计自动化公司，发表有片上扫描链压缩功能的Talus ATPG与Talus ATPGX。这些先进的自动测试向量生成(ATPG)产品使设计师能明显改进测试质量，减少周转时间并且降低纳米级芯片的成本。藉由整合Talus ATPG和Talus ATPGX进入Talus物理设计环境，微捷码提供唯一真正实现物理相关DFT（Physically Aware DFT）的IC实现流程。 今天芯片设计的复杂度和更小的尺寸使测试制作的IC更加复杂。新的失效机制不断涌现。传统上，多数瑕疵是在门级网表上使用由ATPG工具产生的stuck-at模型来检测的。今天要维持必需的百万分之一的瑕疵率(DPM)，IC制造者必须使用与时序、布局和功率相关的瑕疵检验技术。结果，质量测试现在要求使用更多缺点模型以及从各种各样的设计工具中产生的费时和易出错的数据。传统ATPG工具没有这种性能或能力来提供纳米级IC测试质量和周转时间所需的水平。 Talus ATPG设计之初就是为了并行处理多种失效模型，以提高测试质量和设计周转时间。它充分地整合进微捷码的Talus IC实现系统并利用统一的数据模型架构来高效率地得到时间、布局、功率和其它一般ATPG工具无法获得的设计信息。这使Talus ATPG可产生其它工具无法生成的测试向量。例如，Talus ATPG可为极小的桥梁瑕疵和干扰进行测试。使用统一资料模型也允许Talus ATPG支持当前几乎所有的缺点模型，也可以容易地支持未来模型，和提供更好的易用性。 Talus ATPG也包括可在不降低测试质量的前提下进一步减少测试时间和测试费用的额外功能。它是市面上唯一的多线程ATPG工具，可以提供比常规工具更高的吞吐量。Talus ATPGX内建片上扫描链压缩功能，可降低40倍的测试数据容量。Talus ATPG能够准确地诊断机台上的失效以发现瑕疵的逻辑和物理位置。诊断结果可以传递到微捷码的Knights Camelot与Logic Map产品，和从微捷码Yield Manager产品上载的物理和电子瑕疵数据进行交互作用和失效分析。 “随着芯片工艺尺寸越来越小，我们必须处理新的、复杂的错误机制。以传统的ATPG工具来产生测试向量变得更加复杂而费时。”IDT设计自动化服务主任Camille Kokozaki表示，“我们发现微捷码的ATPG，时序和物理布局的紧密结合和无缝流程都非常令人信服。” “作为一个公认的通信技术革新者，我们一直在期待着可帮助我们快速抢占市场的新技术。”Comtech AHA公司工程部副总裁Jeff Hannon表示。“Talus ATPG的多线程引擎，测试向量优化技术，与可针对多缺点模型的能力，使我们可以更快生成更有效的测试向量，有助降低我们先进IC的周转时间和成本。” 随着设计和制造IC的费用日渐增加，测试过程更加高效率是极端重要的-如果您无法测试它，就不要建立它。微捷码设计实施事业部总经理Kam Kittrell表示。Talus ATPG的加入更加强了Talus平台的测试能力，使我们的顾客对他们芯片的制造、测试以及盈利能力更有信心。 Talus ATPG与Talus ATPGX已经上市。 Product:Magma talus 1.0.86a Linux Lanaguage:English Platform:/Linux Size:580MB

Magma Blast 2005.03.170 Linux.Product:Magma Blast 2005.03.170 Linux Lanaguage:English Platform:/Linux Size:455MB

::::::English Description:::::: Catapult is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Catapult is a high-level synthesis tool that uses industry-standard ANSI C++ to generate correct-by-construction, high-quality RTL 10-100x faster than other methods. Unlike traditional RTL design methodologies, Catapult enables the designer to pick the best architecture for given performance/area/power requirement and avoids the design errors introduced from hand coding the RTL description. product:Mentor Graphics Catapult 2008a 39 Lanaguage:english Platform:Winxp/Win7 Size:126MB

明導國際(Mentor Graphics)日前宣佈針對PCB系統設計推出新型Expedition Enterprise 2007.3流程。該流程能夠幫助大型電子公司全面product:Mentor Graphics DXDesigner Expedition Enterprise Flow 2007.3 With Update10 Lanaguage:English Platform:/win2000/winxp Size:900MB

Advanced Design System (ADS) 2009 is a high-frequency/high-speed platform for co-design of integrated circuits (IC), packages, modules and boards. It helps circuit, package, board and system designers work with a single EDA platform to share simulation models and minimize design rework, costs and delays in communications product design. ADS 2009 cuts hardware integration turns by revealing unexpected component interactions upfront that cause integration failures downstream. It offers key enabling technologies for Co-Design, including X-parameters for non-linear modeling of off-the-shelf components through direct measurement; and 3D EM components integrated within the circuit and system design flow. ADS 2009 also interoperates with the Cadence and Mentor back-end design platforms to complete the physical implementation. Product:Agilent Advanced Design System (ADS) 2009 Lanaguage:English Platform:/win2000/winxp...

SystemVue is a focused EDA environment for electronic system-level (ESL) design thatallows system architects and algorithm developers to innovate the physical layer (PHY) ofnext-generation wireless and aerospace/defense communications systems. SystemVuealso provides unique value to RF, DSP, and FPGA/ASIC implementers who rely on signalprocessing to deliver the full value of their hardware platforms.SystemVue replaces general-purpose digital, analog, and math environments by offeringa dedicated platform for ESL design and signal processing realization. SystemVue“speaks RF,” cuts PHY development and verification time in half, and connects to yourmainstream EDA flow.Innovative, easy use model avoids inefficiencies of general-purpose tools• Enhanced simulation is faster, and accounts for more real-world RF effects• Open, polymorphic modeling environment• Access to deep Agilent application knowledge of wireless standards and• communications...

2008.12月下旬发行的最新版本：Mentor Graphics ModelSim SE 6.5 WindowsModelSim专业版,VHDL、Verilog和Mixed-HDL仿真器     Mentor Graphics ModelSim SE 6.5 Windows是业界最优秀的HDL语言仿真器，它提供最友好的调试环境，是唯一的单内核支持VHDL和Verilog混合仿真的仿真器。是作FPGA/ASIC设计的RTL级和门级电路仿真的首选，它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段。全面支持VHDL和Verilog语言的IEEE 标准，支持C/C++功能调用和调试 具有快速的仿真性能和最先进的调试能力，全面支持Windows平台。主要特点：RTL和门级优化，本地编译结构，编译仿真速度快；单内核VHDL和Verilog混合仿真；源代码模版和助手，项目管理；集成了性能分析、波形比较、代码覆盖等功能；数据流ChaseX；Signal Spy；C和Tcl/Tk接口，C调试 product:Mentor Graphics ModelSim SE 6.5 Lanaguage:English Platform:/win2000/winxp Size:208MB

High Performance and Capacity Mixed HDL Simulation – ModelSim Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.ModelSim Spotlight** New Product – ModelSim DE ** With ModelSim DE, we now offer support for Xilinx SecureIP and Assertion-Based Verification with SystemVerilog and PSL support. Find out about Assertion-Based Verification in the Verification Academy. Learn more about ModelSim DE then...

EMPIRE XCcel 5.20 released Nov 2008This new release features the Perfect Geometry Approximation (PGA) method and a comprehensive object libraryProduct:IMST Empire XCcel 5.2 Lanaguage:English Platform:win2000/winxp/win2003 Size:394MB