EDA Design Page 158

Silvaco SIMUCAD Logic 2008.09 WinProduct:Silvaco SIMUCAD Logic 2008.09 Win Lanaguage:English Platform:/win2000/winxp Size:81MB

Mentor Graphics Calibre 2008.3_25.16 Linux Calibre LVS Industry standard physical verification tool for layout versus schematic. Provides method for accurate device parameter extraction with integration to Calibre xRC Allows virtually unlimited capacity for hierarchical designs Offers easy-to-use automatic analysis and optimization of hierarchy for execution efficiency across all design styles Seamless interface within many design environments product:Mentor Graphics Calibre 2008.3_25.16 Linux Lanaguage:english Platform:Winxp/Win7 Size:513MB

::::English Description:::::: Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers...

Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers extensive timing...

::::::English Description:::::: Micro-Cap 9 is an integrated schematic editor and mixed analog/digital simulator that provides an interactive sketch and simulate environment for electronics engineers. Since its original release in 1982, Micro-Cap has been steadily expanded and improved. Micro-Cap 9, the eighth generation, blends a modern, intuitive interface with robust numerical algorithms to produce unparalleled levels of simulation power and ease of use. Nothing else comes close. Faster Algorithmic improvements, optimized code, and an integrated, seamless, analog/digital simulation interface contribute to the stunning speed of Micro-Cap 9.   More powerful Numerous features contribute to Micro-Cap 9 s power. Among them are:   Integrated schematic editor and simulator. Interactive editing and simulation Native digital simulator Transient analysis AC analysis – for investigating...

High-Level Algorithm Implementation for FPGAs and ASICs The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.product:Synopsys Synthesis Tools 2008.09 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:277MB

* Rapidly create and verify technology independent DSP models that are fully portable across vendor and device technologies. * Unique Synplify DSP synthesis engine automatically creates optimized algorithm RTL architectures from your DSP model. * Powerful DSP synthesis optimizations enable exploration of speed/area/device technology tradeoffs without changing your DSP model or verification. * Comprehensive DSP library with full multi-rate support and advanced fixed-pint quantization analysis. * M-Control feature enables use of M-language for concise expression of complex state machine and control logic functionality. * Vector support enables concise expression of parallel and multi-channel algorithms common in wireless and video applications.product:Synopsys Synthesis Tools 2008.09 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:268MB

Lattice Semiconductor (NASDAQ: LSCC) today announced Version 7.2 of its ispLEVER® FPGA design tool suite with advanced place and route algorithms that deliver higher performance results in as much as 30% less time. The ispLEVER 7.2 software also now supports Lattice\’s clock boosting flow for the LatticeECP2™ and LatticeECP2M™ FPGA families. Clock boosting can result in up to a 5% increase in FMax with no additional user input. In addition to performance improvements, ispLEVER Version 7.2 continues to improve designers\’ productivity with additional control, analysis and workflow enhancements, and includes the latest release of Synopsys\’ Synplify Pro® advanced FPGA synthesis solution. “Our ispLEVER design tools continue to evolve in order to satisfy the needs of FPGA designers,” said Mike Kendrick,...

Sisoft Quantum-Sl 2007.08 SP4 provides a truly integrated solution for signal integrity and timing analysis of complex high-speed multi-board systems.   Quantum-SI implements a methodology that encompasses pre-layout and post-layout simulations with rigorous waveform processing, automatically extracting waveform quality reports and interconnect delays. Extracted interconnect delays are utilized by static timing analysis for both synchronous and source-synchronous designs. Quantum-SI provides the flexibility to perform all signal integrity and timing analysis at either the core of the chip, the pad of the I/O, or the pin of the package of both the source and target components. Product:Sisoft Quantum-Sl 2007.08 SP4 Lanaguage:English Platform:/win2000/winxp Size:165MB

::::::English Description:::::: Filter Solutions contains many different types of filters to choose from. Passive, Transmission Line, Active, and Digital IIR and FIR are all supported. See our FIR page for information about our FIR filters that are supported. Analog and IIR filters may all be quickly and easily delay equalized with our real time updates to all pass pole/zero manipulation. Passive and active filters may be quickly and easily modified and reanalyzed with our real time analysis feature. Finite Q may be included in the analysis. Digital filters may be modified and analysis in real time for finite precision analysis. Table one below lists the type of analog filters that are supported along with the parameters that are available for...