EDA Design Page 161

The installation instructions in this document are the most up-to-dateavailable at the time of production. However, changes might have occurred.For the latest installation information, see the product release notes ordocumentation.This document provides instructions for the UNIX, Linux, and Windowsplatforms. The document includes the following sections:Preparing for InstallationInstalling SpiceExplorer and WaveView Analyzer (UNIX and Windows)Invoking SpiceExplorer and WaveView Analyzer on WindowsInstalling the SX-CDS Link PackageInstalling the SX-DAIC Link PackageInstalling the SX-VSDE Link PackageViewing and Printing SpiceExplorer and WaveView AnalyzerDocumentation in Portable Document Format (PDF)Troubleshooting SpiceExplorer and WaveView Analyzer Installation onSolaris PlatformsUninstalling SpiceExplorer and WaveView AnalyzerCustomer Supportproduct:Synopsys SpiceExplorer 2008.03 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:54MB

Synopsys Analysis and Debug products provide a unique approach to transistor-level verification that enables engineers to efficiently analyze and debug complex AMS systems-on-chips (SoCs). CustomExplorer addresses the need for an effective transistor-level debugging environment. The tools provide a netlist-driven debugging and visualization modules, and Custom WaveView with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.product:Synopsys SpiceExplorer 2008.09 Win Lanaguage:english Platform:Winxp/Win7 Size:9MB

he industry\’s first development tool to automatically generate Triple Module Redundancy (TMR) for re-programmable FPGAs. The Xilinx Triple Module Redundancy (XTMR) technology was developed to address the special needs of FPGAs in high-radiation environments. Originally designed for space applications and proven through numerous mission-critical projects, XTMR provides full SEU and SET immunity for any high reliability Virtex®-4 FPGA design.Device Family Support * Virtex-4 * Virtex-II * Virtex System Requirement * Windows 2000/XP Software Requirements * ISE® Foundation™ Software Key Features * Automatically builds XTMR into Xilinx FPGA designs, providing complete SEU and SET immunity * Supports all design entry methods, HDLs, and synthesis tools * Provides optional SRL16 extraction capability * Allows easy integration of custom-built TMR modules * Gives...

Synopsys\’ Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer\’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits * Finds complex bugs, such as those associated with multiple clock domains using static analysis * Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro *...

JMAG-Studio is an electromagnetic field analysis software package developed by JRI Solutions, Ltd. thatsupports the design and development of motors, actuators, circuit components, antennas and other electricand electronic products. It has been supported and used by many companies and universities since 1983.JMAG has a long track record of use for analyzing motors and other rotating devices.JRI Solutions is constantly improving JMAG-Studio by incorporating features suggested in from our usersand by using the latest technology developed through our research and accumulated analysis expertise.Product:JMAG Studio 9.0 Lanaguage:english Platform:Winxp/Win7 Size:144MB

ICX / TAU ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating...

Mentor Graphics日前推出I/O Designer设计工具，据称可以同时进行FPGA和板卡设计。通过I/O Designer，设计人员可以在印刷电路板设计图上分配FPGA针脚信号，当然这需要在FPGA供应商的规则限制下完成。   图形化针脚信号分配可能听起来象一项简单的任务，但其影响非常深远。Mentor表示，在实际产品研究中，使用I/O Designer后优化了电脑主板设计，使路由路线长度减少了超过15%，这将减少设计时间和制造费用。   Mentor公司系统设计部产品开发主管John Isaac表示，“在过去，FPGA设计人员独立完成FPGA设计，然后把设计发给pcb设计师，后者在FPGA针脚信号的选择方面没有主动权。当你对pcb布线时，很有可能要使用更多层和超长的连接线。”   板卡设计师通常没有机会了解FPGA设计规则，获得FPGA各针脚用处的信息。Isaac说，如果一名电脑主板设计师擅自交换了FPGA针脚，结果将会是灾难性的。   但是，I/O Designer自动设计工具可以让主板设计师根据FPGA供应商的约束和规则自主分配针脚。Isaac表示，“pcb设计师可以根据主板情况优化针脚设计，只需要这些设计不超过FPGA器件库的要求。当完成设计后，这些信息会自动发回给FPGA设计系统。”而完成所有这一切，只需要在种图形环境下“拖拉”图标实现。   除图形化分配针脚之外，I/O Designer还可以用FPGA描述自动产生示意图。 product:Mentor Graphics I/O Designer 7.4 Lanaguage:English Platform:/win2000/winxp Size:109MB

Agilent VEE 8.5 New Features•Microsoft® Windows® Vista Support•Modern IDE with dockable tool windows•Newly designed Instrument Manager, Function & ObjectBrowser, and Output Window.•Color Coding•Dynamically change VISA Interface and Address•MATLAB® 2007a Support•Microsoft Office 2007 Support•Using Agilent IO monitor to monitor instant communi-cation•Uncertain data flow compiler warning•Exposing Main from callable server•Microsoft standard file open dialog•Per- user and per- version VEE configuration files•New data type – UInt16 and new execution mode – VEE8.5Product:Agilent VEE Pro 8.5 Lanaguage:english Platform:Winxp/Win7 Size:234MB

MEMS specific layout productivity tools and design verification, 3D model generation and visualization, behavioral model creation and links to 3D analysis packages. Josep Montanyà i Silvestre, CTO at Baolab Microsystems, Terrassa, Spain, says ‘MEMS Pro has been a support for our developments from the very beginning when we started the proof of concept, and it has accelerated our designs allowing us to use a standard IC layout design tool with its DRC capability together with a 3D visualization and a quick connection to standard FEM programs like ANSYS and HFSS.” He added: “MEMS Pro as a tool supporting both IC and MEMS development was a solution natural and easy to implement for us.’ Special features have been integrated into MEMS...

天线建模设计系统 (AMDS) – 一种用于天线及天线系统的 3D 设计与建模专用工具。 AMDS 是唯一能够解决由于消费者审美及功能需求需要更换无线设备问题的 3D 电磁天线设计工具。使用坚定不移的创新技术，在周围的真实环境中高效地引入、网格化及模拟整套无线设备。 使用这套系统，无需进行昂贵的物理测试，您就可以通过关于空中传播性能 (Over-The-Air-performance)、SAR（特定吸收率）及 HAC（助听器兼容性）的法规及运营商兼容要求。   AMDS 是一种独有的 3D 电磁天线设计工具，专门为帮助业内的天线及产品设计人员克服这些挑战而开发。 与同类竞争产品相比，它减少了 70% 后续的建模及模拟设置工作，让模拟成为天线设计人员显而易见的选择。 它在周围真实环境中高效地引入、网格化及模拟整套无线设备，以便分析 SAR（特定吸收率）、HAC（助听器兼容性）及 MIMO（多输入多输出）天线多样性等设备标准。 它使您摆脱缓慢昂贵的物理测试，转而还可以缩短设计周期时间和降低风险。 AMDS 3D 电磁功能组包括： 高效地导入产品设计人员的 CAD 数据，同时降低或减少电磁设计的迭代； 验证天线设备是否符合 SAR、HAC、空中传播性能及 MIMO 等相关法律及运营标准； 通过分析整套物理无线设备的天线放置及多样性，优化 MIMO 性能；以及 通过模拟设备与人体之间的真实互动，优化设备性能。 使用 AMDS，您可以在人头及手的真实远近效果下模拟天线结构及其在设备中的放置，以便确定失谐及灵敏度等参数。这样就可以转化为，既满足相关法规又满足最终用户的性能需求，而不至于陷入延误投放市场时间的原型测试的瓶颈。 Product:Agilent Antenna Modeling Design System (AMDS) 2007.6 Lanaguage:English Platform:/win2000/winxp Size:236MB