EDA Design Page 163

FPGA Design \”Made easy\”Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synthesis and implementation flows, making it a seamless and flexible design and verification platform. Active-HDL supports industry leading FPGA devices, from Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and more. Top Features * Multi-FPGA & EDA Tool Design Flow Manager * Graphical Design entry & editing * Code2Graphics and Graphics2Code * Import/Export Legacy Designs * Pre-compiled FPGA vendor libraries * High Performance Mixed-Language RTL Simulator * IEEE Language Support: VHDL, Verilog®, SystemVerilog Design, SystemC * Automatic Testbench Generation * Advanced Debugging...

Encounter RTL Compiler allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and poweTo maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power. Encounter RTL Compiler, a key component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon. Features/Benefits * A well-balanced logic structure isolates critical paths and reduces power, area, and...

attice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite Tool Suite Includes New 3rd Party Synthesis and Simulator Versions, Integrated ORCAstra Utility and Concurrent LatticeMico32 Release HILLSBORO, OR – SEPTEMBER 8, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 1 for Version 7.1 of its ispLEVER® FPGA Design Tool Suite. The release integrates Lattice\’s ORCAstra configuration design utility, features Reveal™ Logic Analyzer support on the Linux Operating System, adds new versions of Synopsys\’ Synplify® Pro synthesis and Aldec\’s Active-HDL™ Lattice Edition simulator, includes support for automotive temperature grade LatticeXP2™ FPGAs and provides the latest LatticeMico32™ embedded open source microprocessor enhancements. \”This ispLEVER service pack adds a wide range of new utilities...

Flomerics has released Version 7 of its Flotherm electronics thermal analysis software featuring a new Response Surface Optimization capability that Flomerics believes is unrivalled in computational fluid dynamics (CFD) analysis software. Earlier versions of Flotherm included a sequential optimization capability allowing users to specify combinations of design parameters and iterate sequentially towards the best design. The new Response Surface Optimization goes further by fitting a 3D surface to the entire design space, enabling engineers to visualize the complete interaction of the design parameters with the design goal as well as identifying the optimum to a greater degree of accuracy. The user begins Flotherm’s optimization process by defining design goals in the form of a “cost function”, and the ranges over...

JMAG is a simulation software for electromechanical design and development. Many companies and universities have supported and used JMAG since 1983. JMAG can accurately capture and quickly evaluate complex physical phenomena inside of machines. Users inexperience and experienced in simulation analysis can easily perform the simple operations required to obtain precise results. MAG-Designer is a simulation software for electromechanical design striving to be easy to use while providing versatility to support users from conceptual design to comprehensive analyses.Product:JMAG Designer 3.4 Lanaguage:english Platform:Winxp/Win7 Size:474MB

Engineering BaseProduct:Engineering Base 3.1.1.13 Lanaguage:english Platform:Winxp/Win7 Size:816MB

Cadence Incisive Plan-to-Closure Methodology将支持Open Verification Methodology，OVM，OVM基于Cadence的Incisive  Plan-to-Closure URM模块和Mentor的先进验证方法学模块。product:Cadence Incisive Plan-to-Closure Methodology (IPCM) 6.0 Linux Lanaguage:English Platform:linux Size:164MB

PADS®, Mentor Graphics’ world-leading desktop PCB design tool, enables you to develop PCBs within a highly productive, scalable, and easy-to-use environment. PADS solutions cover the spectrum of PCB development, from schematic entry to manufacturing preparation. But, unlike other products, we’re not ‘one-size-fits-all.’ With PADS you buy what you need. PADS Suites, available in three configurations, are our newest solutions, tailored to meet the design needs of each individual.product:Mentor Graphics PADS 2007.3 with update2 Lanaguage:english Platform:Winxp/Win7 Size:565MB

FPGA Advantage is a complete Integrated Design Environment (IDE) targeting high-complexity FPGA device design. The FPGA Advantage IDE spans the RTL FPGA design flow featuring advanced design entry, verification, synthesis and implementation sub-flows. FPGA Advantage accelerates total product design with integration of FPGA IO design as well as bi-directional integration of the PCB design flow. FPGA Advantage provides an integrated HDL flow for designing your FPGAs. FPGA Advantage enables design creation, simulation with debug and analysis, synthesis, management and documentation as a smooth flowing operation from one step to the next. Each component of FPGA Advantage is a proven point tool, but the power comes from integrating these tools tightly together to create a unique HDL design methodology environment for...

Incisive Desktop Manager  Automated verification management Incisive Desktop Manager automates and guides the everyday deployment and visualization of verification tasks and results, increasing engineering productivity and reducing time to market.Cadence® Incisive® Desktop Manager accelerates verification plan execution by automating time-consuming manual tasks at block, chip, system, and project levels. It manages the everyday deployment of common verification tasks, together with visualization of the results. Incisive Desktop Manager also supports a coverage-based verification and debug methodology that increases coverage using incrementally-developed verification plans. Features/Benefits Speeds time to results by automating verification tasks Increases engineering productivity by managing regression tests and failures Enables visualization of coverage results product:Cadence Incisive Desktop Manager (EMGR20) 2.0 Linux Lanaguage:english Platform:Winxp/Win7 Size:397MB