EDA Design Page 164

Cadence® Incisive® Formal Verifier allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits * Speeds time to block design closure with early error detection, analysis, and debug * Reduces risk of re-spin by finding bugs that other verification approaches miss * Eases chip-level verification by delivering higher block-level verification quality * Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies * Supports all industry-standard assertion...

Cadence® Incisive® Enterprise Specman Elite® Testbench uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its functional coverage analysis capability drives verification using the Plan-to-Closure Methodology. Specman technology also supports industry-standard verification languages, compatible with both the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. With the Enterprise System-Level (ESL) Option, Specman technology can be extended to support hardware/software co-verification with pure software simulation-based flows as well as complete “in-system” flows via high-speed links to acceleration and emulation. Features/Benefits * Captures executable specifications to eliminate misrepresentations that can lead...

在采用现有 IP核创建系统级芯片(SoC)时，关键是在设计周期之初，在目标环境中快速地配置和验证IP核。在采用多个IP模块和诸如AMBA的芯片级总线进行设计创建时，设计人员需要能够轻易地完成将多个IP模块连接到总线上并进行配置，从而能够将精力集中在设计中新的逻辑电路上。采用了DesignWare IP 重用工具，IP的创建者可以将自己的IP以某种格式进行打包，这种格式将引导IP集成者完成IP的配置、实现和验证。这样，IP集成者就可以用若干小时，而不是若干天的时间来创建复杂的IP模式和子系统，并开始对它们进行验证，从而大大缩短了整个设计周期。 　　Synopsys为单个IP模块和基于IP的子系统提供了一整套的IP工具，使得IP的创建者和集成者能够轻易地创建和支持复杂的IP。 　　● coreBuilder -将IP有效打包 　　● coreConsultant -引导用户完成IP核的配置和集成 　　● coreAssembler -帮助用户创新和管理打包的基于IP的子系统，包括装配、配置和实现 ::::::English Description:::::: The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge...

Synopsys Liberty NCX 2008.06 sp2 Linux– The Fastest Path to Production Current-Source Libraries Synopsys推出了其库编译器的升级版本，新增了对该公司复合电流源(CCS)模型的支持。该公司还推出了基于CCS的新型库特征化工具集Liberty NCX。 Library Compiler接受开放源Liberty库格式，并将其编译到Synopsys工具的库内。增强功能包括瞄准CCS的质量保证和模型匹配功能。 Liberty NCX士一种取代Synopsys前特征化工具NanoChar的新型库特征化解决方案。与 NanoChar不同，Liberty NCX直接从底至高而构建以支持CCS。此外，Liberty NCX还包含同时特征化合模型精确度验证能力。 当前的电流模型通过使用电流波形取代库内的延迟和偏移值来提高精确度。然而，目前有两种竞争的电流源格式─ Synopsys的CCS，和由Cadence Design Systems 及 Magma Design Automation支持的有效电流源模型(ECSM)。Hoogenstryd指出，Library Compiler能从CCS模型生成ECSM模型。 Liberty NCX面向代工厂、IDM或IP提供商的内部库开发组织。它包括一个模型特征化引擎、一套库质量校验器及模型转换等功能。 The Liberty™ NCX solution is a complete library delivery system specially architected for current-source models that features anoptimized, single-pass Composite Current Source (CCS) library generation flow that performs simultaneous characterization and model accuracy verification. Liberty NCX also includes a suite of library quality assurance, compaction, merging, scaling and adaptation tools. These tools provide unsurpassed flexibility in delivering verified libraries at scaled voltage or temperature corners for tool flows from multiple vendors. Liberty NCX supports all the latest open-source Liberty modeling innovations approved by the Liberty Technical Advisory...

PCBM Matrix IPC-7351A LP Wizard 2009 是IPC7351标准的PCB封装（footpoint/cell）生成工具，用于生成符合DFM要求的PCB封装符号。 ::::::English Description:::::: The IPC-7351A LP Wizard is a fantastic time saver. It is a land pattern calculator based on the IPC-7351A SMT land pattern standard that allows you to define your own CAD land patterns and offers seamless compatibility with the freely-distributed library documentation. Advanced features include:• Graphic display of component features aligned with calculated land pattern • Compensation variables for fabrication and assembly processes• Preset operating environments or user defined goals for land pattern toe, heel and side protrusions• Solder joint analysis calculations• DRC protection from overlapping lands• Automatic land pattern name generation• Save library documentation for later reference/retrieval• Edit part attribute names and values• Easily group parts by project The IPC-7351A...

TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It\’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys\’ patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compact tests for even the most complex designs. PDFDownload Datasheet Key Benefits * Increases product quality with power-aware test patterns for high defect detection * Reduces testing costs through the use of advanced pattern compaction techniques * Increases designer productivity by leveraging integration with Synopsys DFTMAX compression * Creates tests for complex and multi-million gate designs Features * Extremely high capacity and performance * Multicore support for accelerated run...

General verification tips:– Take advantage of the different compare efforts (Low,Med, High, Super, Ultra, Complete).– Handling cell libraries – verify first the library cells andthen use one view for both golden and revised.– LEC parallel compare enables us to reduce thememory load per machine and sometimes it enablesto resolve abort points in that way.Comparing a design in one piece is harder thancomparing all the different pieces one by one.– Use the write hier_compare command to generate thehierarchical comparison script.– This technique is efficient and enables LEC to handlesmaller logic cones at each time.• Due to the nature of our design, LEC will abort when trying tocompare the huge combinational function (the abort point).• Note that recent versions of LEC reducedsignificantly...

Cadence Design System公司日前发布了一种新型形式分析工具，能生成、分析并验证设计师用于运行综合、时序分析和布局布线工具的设计约束(design constraints)的质量。   传统上，用户手动创建设计约束，采用事实上的Synopsys Design Constraint (SDC)标准格式，将它们输入到他们的工具内，运行工具，然后生成违反设计约束的清单。但Cadence高级产品市场经理Ramesh Dewange表示，IC设计日益复杂，需要用户不仅校验HDL和版图的错误，还要验证约束。   “Conformal Constraint Designer是在给定设计问题下确保有效时序约束的产品。它有助于快速时序收敛，并能帮助用户查找出细小的设计约束错误。”Dewange表示。Dewange表示该工具设计用于配合Cadence或第三方的综合、静态时序和布局布线工具使用。   该工具从静态定时器及版图工具读入RTL和门级网表、SDC及可选的关键路径网表。 product:Cadence Conformal Constraint Designer (ccd) v61.Linux Lanaguage:English Platform:linux Size:545MB

Cadence FINALE 6.1 Linuxproduct:Cadence FINALE 6.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:544MB

The Cadence® AMS Methodology Kit employs theCadence Advanced Custom Design (ACD) methodology,which leverages silicon-accurate design methods toenable design teams to create differentiated silicon fasterand with less risk. The kit delivers verified, packagedmethodologies (demonstrated on a real-world mixed-signal design) along with applicability consulting.product:Cadence AMS Methodology Kit 5.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:870MB