EDA Design Page 169

::::::English Description:::::: Digital signal processing (DSP) system design in Altera® programmable logic devices (PLDs) requires both high-level algorithm and HDL development tools. Altera s DSP Builder integrates these tools by combining the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL synthesis, simulation, and Altera development tools. DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. The existing MATLAB functions and Simulink blocks can be combined with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore® functions to link system-level design and implementation with DSP algorithm development. DSP Builder allows system, algorithm, and hardware designers to share a common development platform....

Additional Enhancements to Quartus II Software Version 8.0 * New tasks window: Provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library, including JTAG and SPI interfaces. * Enhanced FPGA I/O planning: Accelerates board development with added pin-swapping capabilities in the Pin Planner. * New IP advisor: Provides design-specific guidelines and recommendations for successful use of Altera’s PCI Express and DDR3 IP. * MegaCore® IP Library: Integrated in Quartus II software, making it easier for users to access Altera’s portfolio of IP cores. New additions with this release include PCI Express Gen2 hard IP, five new video and image...

nLint is a comprehensive HDL design rule checker fully integrated with the Verdi and Debussy debug systems. The Debussy system accelerates users understanding of complex designs to improve design, verification, and debug productivity. nLint adds the ability to fully analyze the HDL for syntax and semantic errors. nLint helps designers create correct HDL code by performing source code checks to ensure conformance with design rules such as synchronous design, clocking scheme, naming conventions, and testability. nLint helps uncovers errors early to reduce simulator, synthesizer, and ATPG run time and to reduce debug time. With nLint, users more easily create readable and maintainable code. They can enforce coding standards across design teams to achieve design re-use goals. nLint operates on design data...

::::::English Description:::::: Novas Design Comprehension Solutions Novas orchestrates a collection of leading-edge solutions that ease design comprehension throughout the verification flow, from systems to silicon.  Our debug systems reduce the time it takes to understand complex logic, giving you more time to spend on adding value to your design. Our new visibility enhancement products optimize verification resources by reducing the amount of data required to gain full visibility into design behavior, cutting simulation and emulation run times, reducing disk space requirements, and enabling effective silicon debug. Novas design comprehension solutions include: Debug Automation to accelerate tracing of causes and effectsProduct:Novas 2007.10 Linux Lanaguage:english Platform:Winxp/Win7 Size:679MB

SPD （Signal Processing Designer）仿真软件是 CoWare Inc.公司的产品，原名为SPW（Signal Processing Worksystem），它提供了面向电子系统的模块化设计、仿真及实施环境，是进行算法开发，滤波器设计，C 代码生成，硬/软件结构联合设计和硬件综合的理想环境。SPW的一个显著特点是他提供了HDS接口和MATLAB接口。MATLAB里面的很多模型可以直接调入 SPW，然后利用 HDS 生成 C 语言仿真代码或者是 HDL 语言仿真代码。SPD 通常可以应用于无线和有线载波通信、多媒体和网络设计与分析等领域。 它还具有以下技术特点： 1、 高效便捷的仿真手段：它用 C 语言开发，仿真效率高，同时，他提供图形化的配置仿真界面，友好的消息显示机制。而且可以在不需要用户干预的情况下进行多速率、动态调度的仿真处理。 2、 多种建模方式支持：只要是 C/C++兼容的建模，系统都可以提供支持，其建模参数可以是 C 兼容的变量表达式语言定义的复杂函数。 3、 大规模的标准数据模型，可支持 XML、关系数据库，并提供 TCL、C++等编程接口。  4、 丰富的构件库，并支持在原有构件库上的编程微调，直接提供 C 源码的编辑和编译环境。 5、 强大的分析和管理工具，可自动生成信噪比曲线，误码率曲线等。 6、 提供从系统建模到芯片级硬件设计的自动化功能。 SPD作为专业的DSP仿真设计开发工具，主要应用在电子设计、通信设计和芯片设计领域，对移动通信系统也提供了强大的支持，适合做底层开发和仿真。但同OPNET一样，它是一款专业性极强的软件，入门难度较高，同时，作为成熟和专业的商业软件，其价格不菲。 ::::::English Description:::::: CoWare Signal Processing DesignerImplementing Algorithms for Platform-Driven ESL Design Highlights Industry s fastest, production proven signal processing simulator Fully supported on Windows and Linux 4000+ models with source code Unique standards reference libraries Fully integrated with MATLAB® and Catalytic MCS tools Fully integrated into CoWare platform-driven ESL design solution RTL cosimulation support for Cadence Incisive® and Mentor Modelsim® RTL code generation for Synopsys DesignCompiler® and Cadence Encounter® Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive® One-click analysis Powerful polymodeling...

Celoxica DK design suite提供以基于ANSI-C的Handel-C语言为基础的高阶设计方法，可在硬件中快速设计和实现复杂的运算法，除了先进的合成及时序评估工具外，DK的区域和延迟分析也可为快速最佳化提供布局前的早期时序和区域评估。该设计工具除了能输出特定FPGA平台EDIF格式外(包含Xilinx,Altera,Actel大部分的芯片)，它能输出结构化的Verilog和VHDL，并保留Handel-C原始码的层次性，因此用户能利用传统的仿真工具来除错Verilog或VHDL输出。HDL输出能用于FPGA/可程序平台，也可用于ASIC工具流程。Celoxica DK将C语言设计到FPGA的流程和方法最佳化，可让软件工程师、硬件设计者及系统架构设计师维持高性能的FPGA方案，并同时加速高可靠性、高速通讯的设计，以及从概念到实现的ASIC替代方案。 ::::::English Description:::::: The DK Design Suite software is a complete ESL design environment for ANSI-C using Handel-C. It provides the benefits of system-level design using C-based design languages to FPGA and SoC. This includes system co-design and co-verification capabilities as well as C-to-RTL and direct C-to-FPGA synthesis. Better designs, faster Specify, design and model systems in C Rapidly explore, simulate and verify diverse HW-SW architectures Find optimal partitions Synthesize directly to FPGA or RTL using the industry’s most widely used C-synthesis technology Algorithm acceleration The DK Design Suite enables designers to quickly and efficiently accelerate software algorithms and system bottlenecks in parallel hardware Sequential C algorithms can be migrated to a parallel hardware implementation using...

::::::English Description::::::  HDL Companion is the HDL designer  Swiss army knife. It will help  you  to get and  keep  a good overview of  any HDL design, including third party  IP, legacy code  and other HDL sources.  Complete design directories and design  files  are dragged and dropped into HDL Companion and a complete design overview is created in seconds, uncovering information regarding numerous aspects of the design. The GUI  offers  many ways to navigate  through the design and explore  the  details you are looking for. Product:HDL Works HDL Companion 2.2 R1 Lanaguage:english Platform:Winxp/Win7 Size:15MB

Green Hills用于PowerPc中支持的源代码级调试器。 ::::::English Description:::::: Green Hills Software provides complete solutions for the development of embedded and real-time applications built on Power Architecture® processors. With our products and services, you can produce totally reliable, absolutely secure, and maximum performance devices—in the least time and with the lowest development and manufacturing costs. Real-time operating systems INTEGRITY® royalty-free, POSIX® conformant RTOS – for total reliability and absolute security. INTEGRITY is used in mission-critical systems such as industrial control, medical devices, avionics, and automotive infotainment platforms. INTEGRITY-178B royalty-free, safety-critical RTOS – Leading securely-partitioned RTOS for safety-critical applications—ARINC 653 compliant, proven in DO-178B Level A certified applications velOSity™ royalty-free RTOS – rapidly develop high performance software using existing BSPs and pre-integrated middleware for microprocessors without...

::::::English Description:::::: SIMetrix/SIMPLIS is a circuit simulation suite optimized for the design and development of electronic power systems. SIMetrix/SIMPLIS comprises the SIMetrix environment with Transim s revolutionary SIMPLIS simulator. Transient analysis 10 to 50 times faster than SPICE – SIMPLIS is a component level simulator like SPICE but simulates power switching circuits typically 10 to 50 times faster. Periodic operating point (POP) analysis POP analysis rapidly locates the steady state operating point of a switching system without having to simulate the startup transient conditions. This considerably speeds the study of effects such as load transients. Small signal AC analysis Unlike the static methods used in SPICE, this analysis mode emulates a frequency sweep measurement as might be conducted on real...

Sandwork设计公司以Spice波形视图工具而闻名的Sandwork设计公司，最近新推出了原理图交互探测(cross-probing)功能并发布了一款增强型可视化调试工具。 SX CDS-Link网络仿真提取(ENS)是Sandwork在现有的CDS-Link中新添的可选项，适合于Cadence设计系统公司的Virtuoso版图环境，并可以提供理想原理图和仿真波形之间的交互探测。这种相关性非常有益，因为在仿真结果中，RC网络名称是随机产生的，所以很难找到相应问题源的原始网络。 ENS选项所增加的功能正是Sandwork公司CEO Jack Yao所提到的“一对多交互探测功能”。以往，用户只能看到与每个原理图对应的一个波形，而现在，一个原理图可以与多个波形相关联。 “在复杂的设计中，当设计人员在布线后(post-layout)进行验证时，他们将面对繁杂的RC网表。”Yao指出，“设计人员很头疼如何才能把理想的原理图同大量的波形数据进行关联。利用该产品，我们能够解决这个问题。” SX CDS-Link ENS的输入包括Cadence原理图和从任何Spice或快速Spice仿真器获得的输出。该产品与被提取出的网表相结合，目前支持Cadence的Assura和Synopsys的RCXT提取工具，还支持详细标准寄生电路格式 (DSPF)。它能对应原理图中的每一个理想网络显示多个波形。 Sandwork还对ChipView进行了增强。ChipView是一个基于布线后RC参数提取DSPF网表的可视化调试产品，它能够自动建立拓扑棍图(stick diagram)来提供一个“伪版图”视图，从“伪版图”提取出的网络可以被映射到原始网络上。 Yao介绍，一个新增加的特性就是在相同网络上，获取从任一提取节点到其它提取节点间的总阻抗的能力。另一项新的特性，是对最有可能出现问题的接地电容和耦合电容进行定位。此外，它还可以对寄生电阻进行彩色编码，以便用户找到最关键的高阻抗器件。 目前，SX CDS-Link ENS和增强型的ChipView都已经开始供货，起价分别为1,400美元和2,200美元。 ::::::English Description:::::: While today’s chip designs demand increasing speed and performance, designers are also faced with the challenge of verifying their chips at both analog and logic levels expediently due to shortened product life cycle. Full-chip simulations require prudent setup and tend to create large amount of simulation data to review. Moreover, typical design process involves iterative simulations – a time consuming process. SPICE Explorer is developed to address the newly arisen necessity for an effective transistor-level debugging environment. The tool is built upon netlist-driven debugging and visualization modules, and WaveView Analyzer with ACE scripting option completes the package. The environment provides front-to-back...