EDA Design Page 173

::::::English Description:::::: The CoreConsole IP Deployment Platform (IDP) and block stitcher has been developed to enable designers to quickly assemble system-level designs and to simplify the construction of a processor subsystem and assembly of IP blocks within a design. The CoreConsole IDP is a front-end design entry tool that enables IP blocks to be stitched together into synthesizable and simulatable RTL that can be exported into Actel’s world-class Libero IDE FPGA development tool suite. The CoreConsole IDP  enables users to focus on the system rather than individual components, allowing them to evaluate system-level performance earlier in the design process and reduce overall development time. Product:Actel CoreConsole 1.4 Lanaguage:english Platform:Winxp/Win7 Size:197MB

Libero IDE offers the latest and best-in-class FPGA development tools from leading EDA vendors such as Mentor Graphics, SynaptiCAD, and Synplicity. These tools, combined with Actel developed tools allow you to quickly and easily manage your Actel FPGA designs. An intuitive user interface and powerful design manager guides you through the process while organizing design files and seamlessly managing exchanges between the various tools. Libero IDE Software Features: Powerful project and design flow management Full suite of integrated design entry tools and methodologies: CoreConsole configured processor and DirectCore IP subsystem creation SmartGen configured common and bus based cores HDL and HDL templates User-defined blocks creation flow for design re-use Actel macro cells ViewDraw Schematic Capture  SmartDesign graphical block subsystem creation...

Actel Libero IDE 8.3 最新释放,Actel创新的SmartDesign功能可简化系统级设计 Actel Corporation 宣布了版本8.3 的它的 Libero 集成设计环境(IDE) 为 FPGA 设计。新版本提供 SmartDesign, 使用户设计在一个更高的水平抽象。新工具随员支持所有Actel 的FPGAs, 包括并且基于闪光的, 低功率ProASIC3 和5 微瓦特Actel 园屋顶的小屋FPGAs, 单片Actel 融合PSC (可编程序的系统芯片) 。 Actel公司为履行其提供和支持高功效解决方案的承诺，全面提升了其Libero集成设计环境 (IDE) 的效能，进一步简化采用其现场可编程门阵列 (FPGA) 产品进行系统级设计的过程。Actel的Libero IDE v8.3现备有名为SmartDesign的全新设计输入项目功能，可让用户在更高的抽象层面完成设计，大大缩短FPGA的设计和开发时间，从而加快客户产品的面市。升级的工具套件支持Actel所有FPGA产品，包括以 Flash 为基础的低功耗ProASIC3和静态功耗仅为5µW的IGLOO FPGA，以及混合信号电源管理FPGA，即单芯片Fusion PSC (可编程系统芯片)。 SmartDesign 是Libero IDE v8.3的一个关键功能，可让用户以图形化方式创建，然后自动抽象出各种基于构件的系统设计并转换成已完成综合 (synthesis-ready) 的VHDL或Verilog部件。这种以图形化方式实现的构件设计输入项目功能支持Actel丰富的DirectCore 和SmartGen IP核库中的各种预制构件，同时也支持采用HDL或 Synplify® DSP生成的用户定制构件，以及用Actel的CoreConsole工具生成的处理器子系统。 Actel产品市场拓展副总裁Rich Brossart称：“Libero以其精确且易于使用的SmartPower功耗分析工具取胜，能协助设计人员应对越来越严格的功耗要求。Libero IDE v8.3工具套件的增强功能代表了我们简化设计和支持高功效应用的最新创新成果。无论用户正在设计ARM处理器、基于Fusion技术的子系统还是使用我们的低功耗IGLOO 器件来设计便携式应用，配有SmartDesign的Libero IDE v8.3均可加快其设计过程，为用户提供能‘正确构建’的保证。” 基于SmartDesign构件的系统级设计环境 创新的SmartDesign具有输入源文件部件的功能，比如将SmartGen和 CoreConsole配置的IP核和处理器核、HDL模块、Actel提供的宏单元，以及Libero生成的构件能以图形化方式组合在一起，并以模块化视图显示在构件视图中的白板“画布” (canvas) 上。SmartDesign提供名为“catalog”的列表功能，能够列出广泛的IP核、宏、HDL模板，以及总线接口；让用户选择所需的元素，然后拖放到“画布”中。因此，SmartDesign利用现有设计的可重用性，为将来采用System Verilog语言、DSP、混合软件/硬件模块来实现的模块化设计铺路。 除了采用SmartDesign设计外，还可通过“SmartGuide”功能为用户建议与设计相配的兼容总线和IP核，这项功能也可用作设计规则检查，确保构建的连接正确。当设计完成后，将生成出已进行综合的HDL源代码文件。由于许多连接都由 SmartDesign中的SmartConnect 功能自动完成，因此Libero IDE v8.3能够为设计人员节省时间和减少错误。 新功能简化Fusion电源管理设计 Libero IDE v8.3加入了升级的FlashPro 6.0软件，为Actel屡获殊荣的混合信号FPGA系列产品Fusion带来额外的支持。配合使用FlashPro 编程器，新版的IDE 软件能够进一步简化Actel的 IGLOO/e、ProASIC3和 Actel Fusion器件的编程。FlashPro中名为FlashPoint的新增功能允许用户独立于Libero 或Designer来修改和编辑FlashROM的安全设置，从而增强设计修改的灵活性。这样，用户就不必通过综合重新运行设计，也省去了布局布线和程序文件生成的工序，大大地缩短了总体的设计时间。 对于Fusion产品，FlashPro的FlashPoint功能可进一步支持用户对Fusion内嵌 Flash 存储器的独立编程。用户可高效地重新编程存储在内嵌 Flash 存储器的电源管理的模拟参数和系统代码。 Product:Actel Libero IDE 8.3 Lanaguage:English Platform:/WinNT/2000/XP Size:760MB

Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus Process is a new-generation process simulator for addressing the challenges found in current and future process technologies. Equipped with a set of advanced process models, which include default parameters calibrated with data from equipment vendors, Sentaurus Process provides a predictive framework for simulating a broad range of technologies from nanoscale CMOS to large-scale high-voltage power devices. Sentaurus Process is part of the comprehensive Synopsys suite of core TCAD products for multidimensional process, device, and system...

Certify® ASIC prototyping solution is the leading product for ASIC prototyping using multiple FPGAs. Certify software combines RTL multi-chip partitioning with best-in-class FPGA synthesis. Using the Certify product makes ASIC prototyping significantly easier, shortens prototype development time, improves prototype performance, and enables faster time-to-market. Synplicity has also updated its Partners in Prototyping program to include new off-the-shelf board and design services companies. Synplicity works closely with these companies to verify interoperability between its own products and the Certify tool in order to develop a smooth flow for ASIC designers, system designers and IP developers. How to Speed ASIC Functional VerificationFunctional verification is considered by many the most time consuming task in ASIC design. Companies often use server farms using dozens...

::::::English Description::::::  Altera delivers all intellectual property (IP) cores, including  the Nios® II embedded processor, in a single MegaCore® IP library package included with the Quartus® II software. Product:Altera Megacore IP Library 7.2 SP3 Lanaguage:english Platform:Winxp/Win7 Size:51MB

XILINX PlanAhead 8.1 Design Analysis Tool AnnouncementFrequently Asked Questions (FAQ)1. What is PlanAhead?The PlanAhead™ Design Analysis tool is logic design and analysis software from Xilinx that is anoptional add-on to the Integrated Software Environment™ (ISE) design tool suite. The PlanAheadtool provides an environment to analyze and floorplan a design targeting any of Xilinx industryleading FPGAs. It offers a powerful enhancement to the ISE development environment, improvingand automating the designer’s ability to analyze and identify performance bottlenecks within theirdesign. With an intuitive environment that provides schematic, floorplan or device views of theirdesign, users can more easily define and refine the hierarchy of their design, allowing for betterperformance and more efficient utilization of device resources.The PlanAhead tool is employed between synthesis and...

Complex Analog/Mixed-Signal System-on-Chip Designs Questa ADMS gives designers a comprehensive environment for verifying complex analog/mixed-signal System-on-Chip designs. ADMS combines four high performance simulation engines in one efficient tool: Eldo® for general purpose analog simulations, Questa® for digital simulations, ADiT™ for fast transistor-level simulations and Eldo RF for modulated steady state simulation. Analog and mixed-signal SoC designs combine analog and digital content more tightly than ever before. They increasingly depend on integrated analog blocks such as A to D and D to A converters, phase-locked loops, and adaptive filters. This increased level of integration puts tremendous pressure on designers. Traditional design tool flows force designers to develop analog and digital subsystems in isolation, delaying the integration of these components until IC...

::::::English Description:::::: Designer – Actel s Design Implementation Software Designer is Actel s powerful physical implementation software tool suite. After completing design entry and functional verification using Libero IDE tools or your favorite front-end design tools, simply import the resulting netlist into Designer to set timing constraints and performing place-and-route, timing analysis, power analysis, and program file generation. Designer provides full power optimization and analysis tools for Actel s low-power flash FPGA families, including the IGLOO/e 1.2 V devices—the lowest power FPGAs on the market. Actel s Designer software offers an easy-to-use design implementation solution for all Actel FPGA devices. It gives you the flexibility either use Libero IDE s integrated tools or other EDA tools from partners such as...

::::::English Description:::::: Designer – Actel s Design Implementation Software Designer is Actel s powerful physical implementation software tool suite. After completing design entry and functional verification using Libero IDE tools or your favorite front-end design tools, simply import the resulting netlist into Designer to set timing constraints and performing place-and-route, timing analysis, power analysis, and program file generation. Designer provides full power optimization and analysis tools for Actel s low-power flash FPGA families, including the IGLOO/e 1.2 V devices—the lowest power FPGAs on the market. Actel s Designer software offers an easy-to-use design implementation solution for all Actel FPGA devices. It gives you the flexibility either use Libero IDE s integrated tools or other EDA tools from partners such as...