EDA Design Page 176

赛灵思(Xilinx)公司发布了其下一代现场可编程门阵列(FPGA)设计和分析工具PlanAhead 9.2.7 Linux。 PlanAhead 9.2.7 LinuxProduct:Xilinx PlanAhead 9.2.7 LINUX Lanaguage:English Platform:/Linux Size:220MB

PlanAhead™ delivers a faster, more efficient FPGA design solution to help find and fix problems early, enabling you to achieve your performance goals.Product:Xilinx PlanAhead 9.2.7 Solaris Lanaguage:English Platform:/Solaris Size:231MB

PlanAhead™ delivers a faster, more efficient FPGA design solution to help find and fix problems early, enabling you to achieve your performance goals.Product:Xilinx PlanAhead 9.2.7 Lanaguage:english Platform:Winxp/Win7 Size:217MB

Mentor Graphics公司日前正式推出Catapult Synthesis Linux，据称这是现今唯一能利用非定时的纯C++语言(untimed C++)来产生高品质寄存器传输级(RTL)描述的算法综合工具，速度最快可达到传统人工方式的20倍。  有了Catapult C Synthesis Linux，硬件设计师就能大幅减少RTL的实现时间，改善设计流程的可靠性，同时将硬件缩小。Catapult C Synthesis Linux用来帮助设计师开发下一代、运算密集型应用的ASIC和FPGA，例如无线通讯、卫星通信和视频图像处理。通过联合系统级设计和硬件设计，Catapult C Synthesis Linux工具结合Mentor Graphics的ModelSim仿真器，可为以C语言为基础的设计流程搭建基本架构。  人工产生RTL的做法已无法应付今日的复杂及高性能设计，原因在于产生和验证RTL电路描述的所需时间，以及原始系统级规格转译过程所可能引入的各种各样的错误。另外，由于人工方法需要耗费大量时间，设计人员无法尝试所有可能的微架构和接口设计，因此只能得到面积和速度次佳的设计；这表明，第一代的行为的和伪定时的(pseudo-timed)方法已无法满足工程师对于快速、高品质设计的要求。  藉由提高抽象级别，并利用通常由系统设计人员产生的相同的非定时的C++原始程序，硬件设计人员现在能自动产生一条精确的、可重复性的途径把C语言模型转变成硬件，且速度远快于传统的人工方法。设计人员只需一套源程序就能产生无错误的流程，它们不但可靠、可重复执行和可重复使用，还能产生专门支持RTL综合工具及厂商工艺的RTL描述。  Catapult C Synthesis Linux可以对核心算法及接口都是非定时的C++源程序进行综合，也是目前唯一具备这项能力的工具，这让设计人员得以针对各种微架构和接口设计执行详细的what-if 分析，进而产生完全最佳化的硬件设计。此工具产生RTL，用标准的RTL综合产品可将此RTL综合成逻辑门，例如用于ASIC的Design Compiler以及支持FPGA的Precision RTL。  爱立信移动平台项目总裁，EDA及设计方法协调人Peter Nord表示，他们能将逻辑门数目减少31%，由于这与硅芯片面积及功耗紧密相关，因此结论不言自明。Mentor与爱立信合作发展以C语言为基础、并能满足爱立信需求的工具，爱立信认为这是非常好的合作经验。  其它高级综合方法是把非定时的C++算法包装至定时的界面，得到一个伪定时的源码，硬件接口被固定编码，不能再改动。Catapult C Synthesis Linux采用正在申请专利的综合技术，它能让非定时的C++源代码完全与硬件接口无关。利用这种创新的技术，设计人员可以快速分析各种性能来取舍，例如应该采用单口存储器还是双口存储器。设计人员不必浪费硅片面积，他们只需利用接口综合，就能正确地将硬件资源与目标接口的可用频宽相匹配，还可透过直观的用户界面来改变约束条件，从一个接口切换到另一个接口。这种方法让同样的源代码能用于各种目的，例如单口存储器、流水数据或是复杂的先进微控制器总线结构(AMBA)总线。  高级综合工具必须有能力为目标工艺和RTL综合工具的关键值建立精确模型，让设计人员在各种微架构之间做出有效的取舍，这是高级综合工具的基础。Catapult C Synthesis利用与其搭配的Catapult C Library Builder工具，可以从带有特定工艺库的后续RTL综合工具里收集详细的特性数据，这使得Catapult C Synthesis能够准确地分配硬件资源，同时迅速提供精确的面积、延时和吞吐量评估，不必花费许多时间和精力去执行整个RTL综合，结果是在更少时间内得到更高品质的设计。Catapult C Library Builder工具还允许设计人员调整定制组件，包含存储器、知识产权(IP)、DesignWare以及现有的RTL。 ::::::English Description:::::: Catapult is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Catapult is a high-level synthesis tool that uses industry-standard ANSI C++ to generate correct-by-construction, high-quality RTL 10-100x faster than other methods. Unlike traditional RTL design methodologies, Catapult enables the designer to pick the best architecture for given performance/area/power requirement and avoids the design errors introduced from hand coding the RTL description. product:Mentor Graphics Catapult Synthesis 2007b...

::::::English Description:::::: The Agility Compiler provides behavioral design and synthesis for SystemC. It is a single solution for FPGA design and ASIC/SoC prototyping. Early TLM models can be quickly realized in working silicon yielding accurate design metrics and RTL for Physical design. Better designs, faster Specify, design and model in SystemC Synthesize high-level models directly to FPGA for verification or RTL for ASIC flows using the industry’s most mature C-synthesis technology System models in silicon earlier Connect the Electronic System Level with Physical design flows using the Agility Compiler Implement Transaction Level Models (TLM) described in SystemC in working silicon much earlier in the design flow. This capability is not restricted to small, single block or single clock domain designs....

The GRASP9 software is the most versatile tool available for analysing general reflector antennas and antenna farms. The package is a general tool to handle single, dual and multi-reflector configurations (beam waveguides). GRASP9 can calculate the electromagnetic radiation from systems consisting of multiple reflectors with several feeds and feed arrays. It is even possible to analyse the interaction between various antenna systems, a requirement which is often encountered in satellite systems where several antennas may be mounted in the vicinity of each other. The scattering from a feed or from a reflector of one system in a reflector of another system can thus easily be calculated. A vast amount of different surfaces, including user-defined shapes, can be analysed, just as...

::::::English Description:::::: Silvaco TCAD Linux  tools start with understanding the physics of the basic semiconductor, dielectric, and conducting materials. The Virtual Wafer Fab technology simulation environment enables the ATHENA process technology simulators and the ATLAS device technology simulators to prepare, run, optimize, and analyze semiconductor experiments to achieve optimal process recipes and device targets. Product:Silvaco TCAD 2006.03 Linux Lanaguage:english Platform:Winxp/Win7 Size:323MB

lvaco TCAD tools start with understanding the physics of the basic semiconductor, dielectric, and conducting materials. The Virtual Wafer Fab technology simulation environment enables the ATHENA process technology simulators and the ATLAS device technology simulators to prepare, run, optimize, and analyze semiconductor experiments to achieve optimal process recipes and device targets.Product:Silvaco TCAD 2007.04 Win Lanaguage:english Platform:Winxp/Win7 Size:271MB

:::::English Description:::::: Innovator is a powerful, fully integrated tool environment for developing, running and debugging virtual platforms. It comes with full SystemC™ (IEEE 1666) support. Its main components are: Schematic system editor, to instantiate, configure and connect IP model components to rapidly build Virtual Platforms Language Editor, to interactively describe behavior of hardware component using a combination of graphical system constructs and ANSI C and SystemC Design Browsers, to quickly reconfigure IP components, to edit run-time scripts and to explore the system connectivity Library Manager, to manage and explore re-usable model libraries Code Generation, to generate optimized C++ code for the graphical language front-end and to seamlessly invoke host compilers to compile the Virtual Platform Hardware debugger, to take run-time...

Simucad is a provider of circuit simulation and CAD software tools used in the design of analog, mixed-signal, and RF integrated circuits. The company was incorporated in Delaware in June 2004 as a spin-off from Silvaco Data Systems.[1] Simucad acquired ownership all of Silvaco\’s simulation and CAD products and intellectual property, most notably the SmartSpice circuit simulator[2]Simucad\’s headquarters are in Santa Clara, California. There are three other direct sales offices in North Chelmsford, MA, Austin, TX, Phoenix, AZ. International sales and distribution is handled through Silvaco\’s existing network of offices in Japan, Korea, Taiwan, China, Singapore and the UK.Product:Silvaco SIMUCAD AMS 2007.04 Win Lanaguage:english Platform:Winxp/Win7 Size:158MB