EDA Design Page 178

:::::English Description::::::   Want a powerful, yet easy to use simulation environment SynaptiCAD s simulation and debugging tools provide a standard interface for controlling all of your simulation tools. SynaptiCAD s timing diagram editors have the most extensive and accurate timing analysis features available in any timing diagram editor on the market including delay correlation, reconvergent fan-out, and clocks that model jitter and buffer delays. Three different levels of editing let you pick the best price and feature set for your application.   Free yourself from the time-consuming process of manually writing Verilog, VHDL, and SystemC test benches. Generate them graphically from timing diagrams. SynaptiCAD provides 3 levels of test bench generation to meet all your design needs. SynaptiCAD offers...

Mentor Graphics TPD translators能够提供PCB 文件和 从Cadstar, OrCad, PCAD or Protel 的footprint libraries到PADS的转换。 ::::::English Description:::::: Mentor Graphics TPD translators Provides translation for PCB Layout files and footprint libraries from Cadstar, OrCad, PCAD or Protel to PADS Layout. product:Mentor Graphics TPD translators Lanaguage:english Platform:Winxp/Win7 Size:26MB

::::::English Description::::::  Mentor Graphics PADS Layout to Expedition Translators 2007  enable PADS files to Expedition files.product:Mentor.Graphics PEX 2007 Lanaguage:english Platform:Winxp/Win7 Size:25MB

::::::English Description:::::: Mentor Graphics I/O Designer provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB. Focused on optimizing system performance, designer productivity and reducing product manufacturing costs, I/O Designer eliminates the barriers between FPGA and PCB flows and design organizations.product:Mentor Graphics I/O Designer 7.2 Linux HDL Lanaguage:english Platform:Winxp/Win7 Size:94MB

hipScope™ Pro tool inserts logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft processors. Signals are captured in the system at the speed of operation and brought out through the programming interface, freeing up pins for your design. Captured signals are then displayed and analyzed using the ChipScope Pro Analyzer tool. The ChipScope Pro tool also interfaces with your Agilent Technologies bench test equipment through the ATC2 software core. This core synchronizes the ChipScope Pro tool to Agilent’s FPGA Dynamic Probe add-on option. This unique partnership between Xilinx and Agilent gives you deeper trace memory, faster clock speeds, more trigger options,...

Leading-edge, real-time debug and verification tools for Xilinx FPGAs enabling on-chip debug at or near operating system speed The complexity of today\’s state-of-the-art FPGAs make it nearly impossible to debug designs using traditional logic analysis methods. Flip-chip and ball grid array packaging don’t have exposed leads for physical probing. Xilinx has the solution: ChipScope Pro. ChipScope Pro inserts logic analyzer, bus analyzer, and Virtual I/O low-profile software cores into your design. These cores allow you to view all the internal signals and nodes within your FPGA, including the IBM CoreConnect Processor Local Bus or On-Chip Peripheral Bus supporting the IBM PowerPC 405 inside the industry-leading Virtex-II Pro FGPA. Signals are captured at or near operating system speed and brought out...

ChipScope™ Pro tool inserts logic analyzer, bus analyzer, and virtual I/O low-profile software cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft processors. Signals are captured at or near operating system speed and brought out through the programming interface, freeing up pins for your design. Captured signals can then be analyzed through the included ChipScope Pro Logic Analyzer. The ChipScope Pro tool also interfaces with your Agilent bench test equipment through the ATC2 software core. This core synchronizes the ChipScope Pro tool to Agilent\’s FPGA Dynamic Probe scope option. This unique partnership between Xilinx and Agilent gives you deeper trace memory, faster clock speeds, more trigger options, all using fewer...

::::::English Description:::::: IC WorkBench (ICWB) is a powerful, hierarchical layout visualization and analysis tool with GDSII/OASIS viewing, layout editing, and high-speed lithography simulation and analysis. IC WorkBench is designed to address a variety of lithographic applications including: Mask Synthesis flow development, OPC model development and calibration, lithography verification error analysis,design rule creation and validation, yield and printability optimization of critical cells, and new process development.IC WorkBench provides qualitative and quantitative information on wafer imaging characteristicsunder varying parameter and process conditions. High Speed, High Capacity Viewing and EditingICWB builds on a solid foundation of fast GDSII/OASIS viewing and editing tool designed to handle the geometrically increasing file sizes of advanced process nodes. ICWB loads gigabytes of data in minutes and has...

::::::English Description:::::: Synopsys?TechXpress™ products enable a revolutionary amount of process insight in a minimum amount of silicon area that is not possible with conventional characterization technologies. A decade of experience in leading-edge technology development and yield optimization has shaped the TechXpress product line to enable the types and volumes of information that are required for successful nanometer-era technology development. Solutions Span Entire Semiconductor Process Life Cycle TechXpress solutions span the entire semiconductor process life cycle. Solutions are grouped into four chip sets that are used by process integration and yield engineers to target the specific tasks found at each stage of the process life cycle. The chips sets are classified as, ToolBox (for early materials and litho characterization), RaceTrack (for...

Synopsys公司发布的针对65nm 和 45nm 设计的电子类软件cadabra。   ::::::English Description:::::: Library developers are facing increasing challenges at the 65nm and 45nm nodes, including increasing design rule complexity, time-to-market pressures, library richness, and late design rule changes. Manual layout is becoming increasingly impractical and expensive. The Cadabra® product offers a fully automated tool for the creation of standard cells layouts from SPICE netlists, and for migration of existing standard cell layouts to new design rules or architectures. With easy to use graphical interfaces and results that rival hand-crafted, the Cadabra product is the market leader in automated standard cell layout. Design Rule ComplexityWith advanced manufacturing processes, the number of design rules that must be enforced for each layer is increasing rapidly. Moreover, many of the newer...