EDA Design Page 182

These errors are typically caused by a problem in the system environment setup. Check your version of System Generator by typing the following at the MATLAB command prompt:>> xlVersion Check your version of MATLAB by typing the following at the MATLAB command prompt:>> ver Check your version of the Xilinx ISE tools by typing the following at the MATLAB command prompt:>> system(\’xinfo\’)and go to the fileset.txt tab to confirm the version listed for each Xilinx tool. Next, make sure you have the latest service packs for all Xilinx tools and double-check that you are using compatible versions of all tools (including service packs and IP updates). See (Xilinx Answer 17966). Finally, check that the following environment variables are set as...

Synopsys Saberproduct:Synopsys Saber 2007.03 linux Lanaguage:english Platform:Winxp/Win7 Size:392MB

RTL (Front End) ToolsProduct DescriptionPlatform Express™, Mentor Graphics’ platform-based design product, enables design creation and verification by automating IP reuse. The product documents all aspects of IP using the IP-XACT™ XML databook format provided through The SPIRIT Consortium. The IP-XACT specification uses XML to create a machine-interpretable IP databook; it includes design information that software tools then use to automatically configure and integrate an IP block into a design. The power of IP-XACT is accessed through generators, which are programs that interpret the IP-XACT data to create design data. Platform Express comes with some of the most sophisticated generators available. These include mixed-language VHDL and Verilog generators that create ready-to-synthesize designs to work on a range of simulators, documentation generators,...

NanoSim™是一个针对模拟、数字和混合信号设计验证的大容量高性能晶体管级仿真器。它是一个稳定而简单易用的工具，为几百万门的片上系统设计提供了较高的仿真能力。对于0.13微米或更小工艺下的设计，它可以达到类似于SPICE的精度。 NanoSim结合了Timemill和PowerMill中最先进的仿真技术，在单独的一个工具里就可以同时完成时序和功耗分析。NanoSim与Timemill、PowerMill完全向下兼容，可以使用同样的网表和初始化设置，可以产生高精度高性能的结果。如果结合使用VCS，它可以在RTL级、门级、晶体管级等各个层次对设计进行仿真。 　　● 对于0.13微米或更小工艺下的设计它可以达到类似于SPICE的精度 　　● 仿真速度大大超过SPICE 　　● 可以仿真大容量的存储器和SOC设计　　● 为混合语言的片上系统设计提供了大量的工具 　　● 支持所有的SPICE网表和模型格式　　● 采用直观的、基于图形化用户界面的初始化配置和仿真环境，非常易于使用 　　● 提供大量内建的时序和功耗分析功能，提高了生产效率product:Synopsys NanoSim 2007.03.Linux Lanaguage:English Platform:/Linux Size:258MB

Synopsys Online Documentation——Synopsys的在线文档。 ::::::English Description:::::: SOLID E3-Dimensional Optical Lithography SimulationSOLID E is a window-based software package for simulating and modeling all the processes and techniques involved in optical microlithography. It is able to simulate the evolution of three-dimensional topographical features in integrated circuit devices throughout the various phases of the microlithography process. Due to its sound physical approach it has a high predictive power, enabling lithography engineers to draw on simulation results to optimize the process technology. This helps to increase the yield and to fully exploit the capabilities of existing equipment. SOLID E is the only lithography simulator on the market capable of simulating wafer topography in three dimensions. SOLID E with M-module – models photomasks and accurately predicts...

::::::English Description:::::: Synopsys’ Leda® 2007.03 is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda抯 pre-packaged rules greatly enhance a designer’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality.   Key Benefits Finds complex bugs, such as those associated with multiple clock domains using static analysis Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro...

The DesignWare Library provides a comprehensive portfolio of synthesizable and verification IP including an AMBA-based on-chip bus solution, memory IP, popular processor cores, bus and I/O standards, and performance enhancing datapath IP elements. The following product documentation is for the DesignWare Library\’s synthesizable and verification IP components. You can access product documentation for the DesignWare digital and mixed-signal IP cores using the “Search for IP” box in the upper right hand corner of this page.product:Synopsys DesignWare.vip Smartmodels 2005.09 Lanaguage:english Platform:Winxp/Win7 Size:101MB

Seamless為MentorGraphic提供的硬體/軟體協同驗證工具，提供高效能和高準確性的軟硬體虛擬平台混合驗證，能降低整合性錯誤的風險並加快產品上市的速度，seamless支擁有業界最大的協同驗證模型資料庫，包括嵌入式設計最常使用的所有架構，而每個 Seamless處理器模組包含一個指令集模擬器，能夠執行組合語言碼和除錯,並提供處理器中的暫存器叢集所有的控制和觀察， Seamless 並有記憶體最佳化技術的專利，這個技術在嵌入式軟體的執行上提供速度上的提昇，並使邏輯模擬器有詳細分析和除錯的功能，配合這些特性 Seamless 可將單晶片系統的測試從硬體雛型系統轉換到虛擬的雛型系統，因此可輕易的更改軟硬體模組，在投入硬體前就能確保軟硬體介面的準確性，大幅的縮短了設計的時程。 Seamless CVE是Mentor Graphics推出的嵌入式系统软/硬件协同验证解决方案。通常，嵌入式软件的开发会滞后于硬件开发，特别是软/硬件的集成调试，必须等到物理原型生产出来以后。所以无法在设计的早期发现软/硬件接口之间的问题。一旦硬件原型有错，修改后还必须从新生产，然后再进行调试。整个设计过程排错困难，周期长，投入高。Seamless CVE将嵌入式软件开发工具和逻辑仿真器结合起来，使项目开发小组在物理原型（电路板或芯片）生产出来之前，就能够使用同一个系统模型进行高性能的软/硬件协同验证，使软件和硬件开发成为并行的过程，从而及早发现并改正软/硬件接口中的错误，缩短设计周期，减少投入。Seamless CVE还可以按照用户的配置来运行，使设计人员既能在需要时观测到所有的软/硬件交互细节，也能通过不同的优化策略来加速软件代码的执行，提高协同验证的效率。　主要特点：　→　缩短嵌入式系统（板上系统和片上系统）的开发周期。　→　减少硬件原型的设计反复次数。　→　加速设备驱动程序和硬件诊断程序的调试。　→　无须更改软/硬件设计。　→　拥有专利的一致性存储器服务器和动态优化技术能够提供最佳的协同验证性能。　→　支持业界主要的微处理器和控制器模型。　→　接口开放，能够集成第三方的设计和验证工具。product:Mentor Graphics Seamless Lanaguage:english Platform:Winxp/Win7 Size:1.27G

Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for Automating Verification of ESD Design Ruleshttp://www.soccentral.com/results.asp?EntryID=29425 Also of interest is the ESDA Symposium in the Los Angeles area (Anaheim to be precise) over the coming week. I’d encourage you to pop in if you can. Last year’s event was our first at the ESDA Symposium, and it was very good. Lots of great...

Dramatically Reduces ASIC Verification Time Compares two designs – RTL to gate for synthesis and ECOs – Gate to gate for layout spins – RTL to RTL for language conversion Highest capacity tool – Verifies multi-million gate ASIC ’s as one Fastest route to correct design – Exact location of errors – Tests fixes within the verification session Where to Use FormalPro : FormalPro is a Regression Testing Tool That verifies all stages of gate-level implementation of a design From synthesis through to tape out Benefits GUI for design entry and initial debug Command line mode for regression testing Constraint language and TCL scripting Incremental Verification Recompile only design that has changed Restart at intermediate pointsproduct:Mentor Graphics FormalPro 2006.1_1-3 Linux...