EDA Design Page 183

Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced the availability of advanced device parameter measurement functionality in its Hercules(TM) Physical Verification Suite (PVS). Developed to support the latest release of 65-nanometer (nm) design kits from IBM (NYSE: IBM), this new functionality enables IBM foundry customers using the Hercules layout versus schematic (LVS) rule files in the kit to easily and accurately correlate device behavior to the IBM process. These IBM foundry customers also have access to the latest Hercules design rule checking (DRC) as part of the 65 nm design kit release. These files are qualified for accuracy and optimized for performance. “We have been supporting Synopsys Hercules PVS for over a decade,” said Dave Harame, director...

DiscoveryTM Pioneer-NTB是一套功能全面的SystemVerilog测试平台自动化工具，可与流行的VHDL和Verilog仿真器配合使用。Pioneer-NTB能够让工程师在混合仿真环境中方便地应用先进的基于开放标准的验证方法。Pioneer-NTB是在Synopsys® VCS®全面RTL验证解决方案中各项功能强大并经产业证实的技术以及Vera®测试平台自动化工具的基础上开发而成，提供了即时获得由VCS和Vera构成的广泛的体系的能力。Pioneer-NTB还支持OpenVera®语言，能够让现有Vera验证环境容易地移植到Pioneer-NTB上，并可实现高达2倍的验证运行时间性能提升。[img]http://www.synopsys.com.cn/synopsys/products/images/Discovery-009.gif[/img]主要优势　　● 支持SystemVerilog验证功能，从而可以采用基于面向对象、先进的数据类型、约束随即激励、功能覆盖以及断言等技术来创建高效的测试平台环境。　　● 支持Synopsys的参考验证方法学（RVM），并包括了基本模块库，从而加快了按照业界最优做法来实现覆盖率驱动、约束随机和基于断言验证等技术的鲁棒且可重用的验证环境的开发过程。　　● 内置、完整地支持了SystemVerilog断言（SVA），并且拥有一个包括50多个可用的检查器库，以及一个包括多种流行接口协议标准的断言IP库，从而可以实现基于断言的可验证设计（DFV）方法的快速投入应用，加快设计错误检测的速度，改善设计方案质量　　● 内置功能和断言覆盖率以及统一的覆盖率报告功能，对验证目标的达成度提供综合全面的观察　　● 本征、快速地支持高质量验证IP的VCS验证库，能够加快大范围采用了标准接口协议的设计的先进验证环境的开发和执行速度。　　● 对于OpenVera语言的深入支持，让Vera语言使用者能够很容易地将现有的验证环境移植到Pioneer-NTB上，并实现高达2倍的性能。product:Synopsys Pioneer-NTB SystemVerilog Testbench 2006.06 Linux Lanaguage:English Platform:/Linux Size:319MB

一款在HDL.Designer.SeriesHDL.Designer.Series软件中使用FPGA/PLD/HDL设计工具。product:Mentor Graphics DesignAnalyst 2005.1 FPGA/PLD/HDL设计 Lanaguage:English Platform:/WinNT/2000/XP Size:28MB

在将具有竞争性、不同凡响的产品推向市场的设计过程中，可测性设计日益变得重要起来。从没有“放之四海皆准”的测试方案，这就是为什么Mentor Graphics推出广泛的DFT工具的原因。这些世界领先的工具缩短了设计开发时间，并保证更高质量。所有这些都比现在其它任何DFT工具的风险小。我们的DFT服务队伍会帮助你轻松地进行测试点插入，测试矢量生成和故障仿真，保证在你的设计限制范围内达到最高的测试覆盖率。 Comprehensive DFT Solution for SOC Designs DFT process in ASIC design flow DFT(Design-For-Test)是Mentor Graphics公司的黄金产品，该产品在近三年来一直独居技术、市场世界第一。该产品之所以具有如此的地位，关键在于以下两方面: ASIC设计师公认测试、综合在ASIC设计中同等重要；Mentor Graphics有着高水平研发队伍，总能使自己超前发展。如图所示为一个完整的测试解决方案，这样的解决方案包含边界扫描设计(Boardary Scan)，内部全扫描(Full Scan)或部分扫描设计(Partial Scan)，自动测试向量生成(ATPG)，存储器内建自测试(Memory BIST)，以及逻辑内建自测试(Logic BIST)的设计技术。测试是非常复杂的问题，Mentor Graphics公司主张不同类型的测试问题，应选用不同的工具去解决。这样方能保证精确有效的测试结果。 [img]http://cn.sun.com/isv/solutions/images/mentor-2_01.gif[/img] [img]http://cn.sun.com/isv/solutions/images/mentor-2_02.gif[/img] 确保设计能于制造后正确工作 DFT工具为设计的可测性增加了设计电路（RTL或者gate level） DFT工具为投入生产的设计生成测试组来检测其缺陷 基于DFT结果进行失效分析 [img]http://www.mentorg.com.cn/images/products/test_Insert.gif[/img]product:Mentor Graphics Design-For-Test(DFT) 2006.3.10 可测性设计 Lanaguage:English Platform:/Linux Size:197MB

>::::::English Description:::::: Raphael is the gold standard, 2D and 3D resistance, capacitance, and inductance extraction tool for optimizing multi-level interconnect structures and on-chip parasitics in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide. Benefits Analyze complex on-chip interconnect structures and the influence of process variation Create a parasitic database for both foundries and designers to study the effect of design rule change Generate accurate capacitance rules for layout parameter extraction (LPE) tools product:Synopsys Raphael 2006.12 Linux Lanaguage:english Platform:Winxp/Win7 Size:36MB

FEATURED TECHNOLOGY CustomSim Circuit SimulationUnified AMS verification technologies deliver 4x performance improvement VCS Multicore Technology2x verification speed-up on complex designs Lynx Design SystemThe Lynx Design System is a highly automated, production-ready, chip implementation platform. Power-Aware TestBreakthrough technology in DFT MAX compression and TetraMAX ATPG. SuperSpeed USB 3.0Learn about USB 2.0 vs. 3.0 and how to evaluate a USB IP solution.product:Synopsys Circuit Explorer 2006.03 Linux Lanaguage:english Platform:Winxp/Win7 Size:62MB

[img]http://www.mentorg.com.cn/images/products/pcbsystem.gif[/img] The Board Station® family of products continues to provide loyal users with constant infusions of productivity-enhancing and groundbreaking technologies all without interrupting the massive, high-volume businesses that create the most adopted technologies and leading products that shape our world today. There is an exciting new flow available to Board Station users called Board Station XE. This new flow enables the highly productive design of complex PCBs through modern and innovative design tools to meet a customer’s need to reduce design cycle times, build more complex systems and utilize new PCB manufacturing techniques. It also enables existing Board Station customers to: Leverage existing libraries, library infrastructure and front-end design tools Minimize costs normally associated with deploying a new flow Reduce...

Mentor Graphics EN 2004 * Mentor Graphics SDD 2004 * Mentor Graphics WG 2004 * Mentor Graphics DMS 2004 * Mentor Graphics eProduct Designer(Mentor Graphics ePD), * ICX/Tau * Quiet Expert 这些都集成在一个独立的Integrated Systems Design (ISD)产品中. Mentor Graphics ISD 2004 SPac4英文描述: Name: Integrated Systems Design : 2004 Service Pack 4 Description: We are now providing a single-launch install process for all System Design Division (SDD) products using the new Mentor Graphics Standard Installation (MSI) program. That is, we combined the EN, SDD, DMS, WG, ePD, ICX/Tau, and Quiet Expert releases into a single Integrated Systems Design (ISD) Release. You simply choose the products you desire and MSI installs that version of the product.product:MENTOR GRAPHICS ISD2004 Spac4 Lanaguage:english Platform:Winxp/Win7 Size:1.48G

::::::English Description:::::: FPGA Compiler II Release Notes ——————————————————————————– These release notes present the latest information about FPGA Compiler II version T-2003.09 FC3.8 in the following sections: New Features, Enhancements, and Changes Resolved STARs For information about earlier releases of FPGA Compiler II, log on to SolvNet. To access SolvNet, Go to the SolvNet Web page at http://solvnet.synopsys.com. If prompted, enter your user name and password. (If you do not have a Synopsys user name and password, follow the instructions to register with SolvNet.) Click Release Notes in the column on the left side of the SolvNet Web page. New Features, Enhancements, and Changes FPGA Compiler II version T-2003.09 FC3.8 provides new features, enhancements, and changes as described in the following...

NanoSim™, an advanced circuit simulator for memory and mixed-signal verification, combines best-in-class simulation technologies from TimeMill® and PowerMill® to deliver an unparalleled combination of timing and power analysis and diagnostics in a single tool.product:Synopsys NanoSim 2006.06 Lanaguage:english Platform:Winxp/Win7 Size:569MB