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Cadence INCISIVECadence Design Systems, Inc., a leader in global electronic design innovation, introduced its leading functional verification platform and methodologies, INCISIVE 15.20.As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.Core engines include JasperGold formal...

Mentor Graphics Tessent 10.7 The Tessent® Product Suite The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.Tessent Product AreasAutomotive The rapid growth in automotive ICs has ushered in a new era in semiconductor test. Both device suppliers and integrators are scrambling to understand and define critical quality and reliability requirements and implementation solutions. Tessent Automotive can help.Logic Test Mentor Graphics offers the industry’s most powerful suite of logic test solutions with more than two decade of successful...

Cadence.IC.Design.Virtuoso.06.17.721.Hotfix.Only.Linux 1DVDFor the builders of tomorrow, creating the electronic systems that enable smart living will require advanced design technologies on multiple levels—semiconductor, chip packaging, system interconnect, hardware-software integration, system verification, and more. Past approaches to design that address these levels disjointedly are inadequate for the increasing complexity, low-power requirements, and shorter time-to-market challenges that designers face today. Successful companies will thrive by collaborating with ecosystem leaders in electronic design automation, intellectual property, chip fabrication, and other parts of the value chain to create a comprehensive environment for System Design Enablement (SDE). Cadence® custom/analog/RF solutions are a key component of the SDE strategy. Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit...

Cadence Xcelium v18.03.001 Linux Key Benefits Provides an average 2X improved single-core performance Offers an average multi-core performance speed-up of 3X for RTL design simulation, 5X for GLS, and 10X for DFT simulations running on today’s servers Provides parallelism with multi-core speed-up, benefiting event-dense simulation runs of all types Further extends innovation within the Cadence Verification Suite Support expands from x86 CPUs to include Arm-based servers Cadence® Xcelium™ Parallel Logic Simulation is the EDA industry’s first production-ready third-generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster than current solutions. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation simulators. The...

Cadence ASSURA 6.16.04.14.001 Key Benefits Trusted custom/analog signoff for mature nodes Integrated with Virtuoso AMS/custom design and simulation technologies Decreases overall DRC/LVS signoff iterations with an intuitive Virtuoso platform-based debug environment Cadence® Assura® Physical Verification supports both interactive and batch operation modes with a single set of design rules. The tool uses hierarchical- and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification is supported where foundry rule decks are available. Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and...

RSoft Optsim System Suite 2018.03 OptSim Product Overview RSoft OptSim™ is an award-winning software tool for the design and simulation of optical communication systems at the signal propagation level. With state-of-the-art simulation techniques, an easy-to-use graphical user interface and lab-like measurement instruments, OptSim provides unmatched accuracy and usability. The software has been commercially available since 1998 and is in use by leading engineers in both academic and industrial organizations worldwide. Layout of a 111 Gbps dual-polarized QPSK system with coherent receptionBenefits Virtual prototyping of optical communication systems for increased productivity and reduced time to market. Design optimization for enhanced performance and reduced costs. Interfaces with third-party tools such as MATLAB and the Luna Optical Vector Analyzer. Advanced electrical modeling with...

Keysight EMPro 2017 Update 0.1Keysight Technologies Inc. has released an update to EMPro 2017. This release delivers several FEM mesher and solver improvements resulting in faster simulations, as well as new parameterization capabilities, enhanced visualization and improved python scripting. EMPro 2017 Update 0.1 Release Notes: Issue Addressed EMPro– A python function (Assembly._setitem_) that was no longer available in EMPro 2017 has been restored.– Fixed an issue that could cause EMPro to hang while saving a project.FEM– Fixed an issue in the FEM mesh refinement process when objects of the same materials are merged.– Fixed a remote FEM simulation license issue.– Reduced the memory consumption of FEM simulations for large designs with many ports. This may increase the simulation time by...

Synopsys Formality vO-2018.06 SP1 Formality and Formality UltraVerifies the Toughest Designs Synthesized with Design Compiler Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all DC Ultra and Design Compiler Graphical optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality Ultra adds innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs...

Accelerate Innovation withDesign Compiler Graphical “With Design Compiler Graphical, we are experiencing 10% faster timing and very tight correlation to IC Compiler…Design Compiler Graphical has also helped us reduce area and is now a standard component of our design flow.” — Mellanox TechnologiesAccelerate Design Innovation and Maximize Productivity Synopsys\’ Design Compiler family of products maximizes productivity with its complete solution for RTL synthesis and test. Design Compiler Graphical uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best-in-class quality-of-results at all process nodes. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. The Design Compiler family also includes the award-winning synthesis-based test solution for...

Synopsys IC Compiler vO-2018.06 for linux IC CompilerPlace and Route System The IC Compiler™ place and route system is a single, convergent, chip-level physical implementation tool. It includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs. For Synopsys’ latest place-and-route system refer to IC Compiler II. IC Compiler is a complete place-and-route system for established and emerging process technology node designs. IC Compiler hierarchical design technology enables powerful design planning and early chip level exploration/analysis features to handle large, complex designs. IC Compiler delivers smaller die size with predictable design closure to reduce the cost of design. IC Compiler with Zroute digital router technology...