EDA Design Page 96

Antenna Magus Professional has a broad selection of antenna designs included in the database which is continually being expanded with new designs. Regular updates of the software as well as the database will be available under the downloads page. Users can search through the database by entering search criteria consisting of keywords like high gain, wide band, circularly polarised etc. and select and design antennas according to performance objectives. The designed antennas can be analysed in Antenna Magus to give a quick approximation of the antenna\’s performance. Once the user is satisfied he can export his design as a parameterised model to any of the supported analysis toolsProduct:Antenna Magus Professional 5.0.1 Lanaguage:english Platform:Win7/WIN8 Size:615 MB

Synplify Pro® FPGA synthesis software, part of the Synopsys FPGA design solution, is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Lattice Semiconductor, Microsemi (formerly Actel), SiliconBlue and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the...

Encounter Conformal Equivalence Checker Formal verification technology for fast and accurate bug detection and correctionCadence® Encounter® Conformal® Equivalence Checker (EC) makes it possible to verify and debug multi-million–gate designs without using test vectors. It offers the industry’s only complete equivalence checking solution for verifying SoC designs—from RTL to final LVS netlist (SPICE)—as well as FPGA designs. Encounter Conformal EC enables designers to verify the widest variety of circuits, including complex arithmetic logic, datapaths, memories, and custom logic.Already proven in thousands of tapeouts, Encounter Conformal EC is the industry’s most widely supported independent equivalence checking product. It is production-proven on more physical design closure products, advanced synthesis software, ASIC libraries, and IP cores than any other formal verification technology. Benefits Exhaustively...

Cadence Physical Verification System (PVS) integrates with industry-standard Cadence Virtuoso® custom/mixed-signal and Cadence Encounter® digital design flows. This provides designers with an end-to-end design and signoff solution from a single vendor. PVS is a trusted solution that enables users to achieve advanced node design signoff in a quick total turnaround time. It provides efficient, effective debug tools to reduce debug time and increase productivity. This solution supports advanced process node technology (such as double patterning, 3D-IC, and advanced device extraction), and it extends physical verification technology into design reliability checking and constraint validation. PVS also offers a distributed multi-threading processing capability that greatly accelerates throughput without requiring specialized hardware. Benefits Trusted solution with production-proven accuracy Single-vendor solution for implementation and...

Cadence® Assura® Physical Verification supports both interactive and batch operation modes with a single set of design rules. It uses hierarchical processing and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification incorporates advanced sub-65nm process parameter measurement, nanometer design rules for DFM, and process design rule checks. Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® custom design environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration with transistor-based...

Advanced Simulation Technology Using sophisticated resolution techniques, Eldo Premier goes beyond the status quo to accelerate the transient simulation of large circuits both pre and post-layout without sacrificing accuracy. Producing the same \”golden\” results as Mentor\’s industry leading SPICE simulator, Eldo Classic.Optimized for Single and Multi-Threaded Application The acceleration of single-thread simulation is provided by new algebraic techniques for the resolution of the system of non-linear differential equations that analog simulators must solve. The acceleration of multi-threaded simulations is a consequence of the natively parallel code of the new Eldo Premier simulation kernel and its dedicated data structures. These two acceleration factors naturally combine to offer a very significant speed-up over Eldo Classic.Dramatically Improve Design Team Productivity Boosting performance over...

GoldenGate RFIC Simulation Software GoldenGate RFIC Simulation and Analysis Software is an advanced simulation and analysis solution for integrated mixed signal RFIC designs that is fully integrated into the Cadence Analog Design Environment (ADE). GoldenGate is part of Agilent\’s RFIC simulation, analysis and verification solution that also includes Momentum for 3-D planar electromagnetic simulation, SystemVue & Ptolemy wireless test benches for system-level verification, and the Advanced Design System (ADS) Data Display for advanced data analysis. This suite links the RF system, subsystem, and component-level design and analysis as part of a unique and comprehensive RFIC design flow.Key Benefits of GoldenGate Best performance, capacity and accuracy to complete your RFIC designs on time with the highest level of designer productivity Delivers...

Agilent Technologies Inc. (NYSE: A) today announced the latest release of Genesys 2014, its industry-leading, affordable RF simulation and synthesis software. Designed for circuit and system designers, the Agilent EEsof EDA software features breakthrough modulated RF analysis as well as enhancements to its powerful, custom-filter direct synthesis technology. Using Genesys 2014, designers can now simulate digitally modulated RF signals like those found in today\’s defense and consumer wireless applications as easily as they do traditional analog RF signals. Unlike other simulators that provide only single-value results for EVM, BER or ACPR, Genesys 2014 delivers breakthrough system budget analysis of these digital modulation metrics for every component in the system block diagram, all in a single pass. This provides RF designers...

YDC offers the CAD system for electronic design that meets the needs of the customer\’s eternal theme in electronic design, that is, \”time to the market, high quality, and high reliability\”.\”CADVANCE\”, which was developed first in 1982 spending all one\’s energy of the YOKOGAWA group, is the CAD system that has been enhanced to meet a large number of requests from the customers and to support the latest technologies for many years since its first release.Schematic design system with advanced capabilities to recognize logics and link closely with relevant applications The system supports the integrated design environment (IDE) that provides the user with advanced operations. Docking windows, switching windows by tab, and intuitive user interface are adopted. These assist the...

Incisive Enterprise Simulator Multi-language simulation fuels testbench automation, low-power, metric driven verification, and mixed-signal verificationIncisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization. IES is the core engine for low-power verification working closely with Conformal LP, the digital engine for mixed-signal verification working with Virtuoso simulators, the testbench engine for simulation acceleration with Xtreme and Palladium, and the RTL engine working with TLM verification solutions.When digital simulation became commonplace in the 1980s, flows were simple: RTL, then gate, then implement. Since then, simulation has matured into verification and has become the critical means to enable productivity, predictability, and quality in complex FPGAs, ASICs, and...