Tags :Aldec

Functional Verification Verification-Platform-Grows-01.jpgRiviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.Top Features and Benefits High Performance Simulation Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems Support for the latest Verification Libraries, including Universal Verification Methodology (UVM) Advanced Debugging Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs quickly UVM Toolbox, UVM graph, Class Viewer, Transaction...

Aldec, Inc., announced today the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment and new support for SVA and PSL assertions in the Waveform Viewer. Riviera-PRO supports System Level Verification with SystemC and SystemVerilog, Assertions based verification, Open Verification Methodology (OVM), Electronic System Level (ESL) and STARC® based Linting. Verilog Simulation Performance Speed-upVerilog simulation speed at the gate level has been increased up to 2.3X over the previous release. Memory allocation during simulation has been significantly reduced, to enable larger solutions on 32 and 64 bit platforms. All mixed language designs...

ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, clock and reset issues prior to simulation and synthesis. Powerful, graphical utilities are provided for violation analysis and debugging. ALINT significantly reduces verification time for complex FPGA and ASIC designs, which results in uniform, reusable and reliable code, reducing the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. User-definable rules and extensive rule management features enable corporate standardization. Top Features * Fast design analysis of complex ASIC/FPGA/SOC designs * IEEE VHDL, Verilog and mixed-language designs * STARC VHDL or Verilog rule...

FPGA Design \”Made easy\”Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synthesis and implementation flows, making it a seamless and flexible design and verification platform. Active-HDL supports industry leading FPGA devices, from Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and more. Top Features * Multi-FPGA & EDA Tool Design Flow Manager * Graphical Design entry & editing * Code2Graphics and Graphics2Code * Import/Export Legacy Designs * Pre-compiled FPGA vendor libraries * High Performance Mixed-Language RTL Simulator * IEEE Language Support: VHDL, Verilog®, SystemVerilog Design, SystemC * Automatic Testbench Generation * Advanced Debugging...