Tags :Cadence tutorials

Cadence GENUS 16.2 Key Benefits Up to 10X better RTL design productivity Up to 5X faster turnaround times, with linear scalability beyond 10M instances At least 2X reduction in iterations between unit-, block-, and chip-level synthesis Timing and wirelength within 5% of place and route in the Cadence Innovus Implementation System Up to 20% reduction in datapath area without any impact on performance The ultimate goal of the Cadence® Genus™ Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design and the highest quality of results (QoR) in final implementation. The Genus synthesis solution provides up to 5X faster synthesis turnaround times and scales linearly beyond 10M instances. In addition, a new physically aware context-generation capability...