Tags :coretools 2014

Synopsys coreToolsIP Based Design and VerificationOverviewThe Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools foruse in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gainswhen using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the riskconfiguration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction inSoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge and design intent of the IPand provide graphical or command based configuration menus for the...