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::::::English Description:::::: Mentor Graphics I/O Designer 7.3 provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB. Focused on optimizing system performance, designer productivity and reducing product manufacturing costs, I/O Designer eliminates the barriers between FPGA and PCB flows and design organizations.product:Mentor Graphics IO Designer 7.3 with UPdate1 Lanaguage:english Platform:Winxp/Win7 Size:179MB

OverviewWith process geometries reaching90-nanometers (nm) and below, thereare many nanometer effects that canimpact timing. Accurate analysis ofthese effects is required to identify realtiming issues.Synopsys’ NanoTime tool is thenext-generation transistor-levelstatic timing analysis solution thataddresses the emerging challengesin signal integrity (SI) analysisassociated with custom designs.NanoTime offers concurrent timingand SI analysis, accuracy withinfive percent of HSPICE®, and theperformance required to analyzecomplex transistor circuits overnight.Its seamless integration with Synopsys’PrimeTime® product enables full-chipanalysis of designs that includes bothgate- and transistor-level blocks.NanoTime is a key component of theSynopsys custom design verificationsolution that includes CustomSim®and HSPICE for circuit simulationand ESP-CV for symbolic simulation.product:Synopsys Nanotime 2007.12 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:81MB

IC-CAP 2008 (with Add-ons 1 & 2): Bringing Innovative Modeling Technology to Our Customers The IC-CAP 2008 release introduced the IC-CAP Target Modeling Package. Used to extract MOS models from semiconductor manufacturing process targets, the Target Modeling Package enables designers the to develop device simulation models earlier in the design cycle for faster overall integrated circuit design. The IC-CAP 2008 Add-On 1 release introduced the Hisim2.4 Model Extraction Package, an easy-to-use and efficient flow to measure and extract DC and RF parameters of the Hisim2.4.1 model. The IC-CAP 2008 Add-On 2 release introduced a similar extraction package for the Hisim_HV model for symmetrical HVMOS and asymmetrical LDMOS devices. New with this Release * Target Modeling Package * HiSIM2.4 Model Extraction...

FPGA Design \”Made easy\”Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synthesis and implementation flows, making it a seamless and flexible design and verification platform. Active-HDL supports industry leading FPGA devices, from Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and more. Top Features * Multi-FPGA & EDA Tool Design Flow Manager * Graphical Design entry & editing * Code2Graphics and Graphics2Code * Import/Export Legacy Designs * Pre-compiled FPGA vendor libraries * High Performance Mixed-Language RTL Simulator * IEEE Language Support: VHDL, Verilog®, SystemVerilog Design, SystemC * Automatic Testbench Generation * Advanced Debugging...

attice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite Tool Suite Includes New 3rd Party Synthesis and Simulator Versions, Integrated ORCAstra Utility and Concurrent LatticeMico32 Release HILLSBORO, OR – SEPTEMBER 8, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 1 for Version 7.1 of its ispLEVER® FPGA Design Tool Suite. The release integrates Lattice\’s ORCAstra configuration design utility, features Reveal™ Logic Analyzer support on the Linux Operating System, adds new versions of Synopsys\’ Synplify® Pro synthesis and Aldec\’s Active-HDL™ Lattice Edition simulator, includes support for automotive temperature grade LatticeXP2™ FPGAs and provides the latest LatticeMico32™ embedded open source microprocessor enhancements. \”This ispLEVER service pack adds a wide range of new utilities...

Cadence® Incisive® Formal Verifier allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits * Speeds time to block design closure with early error detection, analysis, and debug * Reduces risk of re-spin by finding bugs that other verification approaches miss * Eases chip-level verification by delivering higher block-level verification quality * Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies * Supports all industry-standard assertion...

MoldWorks 2008 SP1 includes RTI catalogue and support for Vista Product:MoldWorks2008 SP1.0 for SolidWorks Win32 Lanaguage:english Platform:Winxp/Win7 Size:134MB

TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It\’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys\’ patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compact tests for even the most complex designs. PDFDownload Datasheet Key Benefits * Increases product quality with power-aware test patterns for high defect detection * Reduces testing costs through the use of advanced pattern compaction techniques * Increases designer productivity by leveraging integration with Synopsys DFTMAX compression * Creates tests for complex and multi-million gate designs Features * Extremely high capacity and performance * Multicore support for accelerated run...

Cadence FINALE 6.1 Linuxproduct:Cadence FINALE 6.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:544MB

ICEM Surf provides breakthrough technology enabling users to produce world-class aesthetic products in today\’s competitive, global markets. Acknowledged as the premier system for the creation and development of Class A surfaces, ICEM Surf bridges the demands of aesthetic designers and production engineers from visualisation right up to tool and die designers. The flexibility of ICEM Surf results in high-quality surfaces required in today\’s design environment, while substantially reducing overall design time. Product development teams using ICEM Surf leave the traditional process behind. ICEM Surf\’s integrated solutions enable users to implement a new, more efficient method of product development called Virtual Modelling. Stylists and engineers work out design treatments dynamically on screen and immediately see the aesthetic, as well as the...