Analog/mixed-signal extractor; provides high-speed parasitic extraction on full-chip layouts with silicon accuracy; part of the silicon analysis function inside the Virtuoso® custom design platformproduct:Cadence Assura 3.17-5141 Linux Lanaguage:english Platform:Winxp/Win7 Size:1.43G
Cadence IUS is the Incisive Unified Simulator which is used in classes such as ECE130 and CSSE232. This software allows you to perform behavioral simulation on Verilog and VHDL code.product:Cadence IUS 8.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:1.81G
::::::English Description:::::: GEOPAK Site provides a visual, interactive environment for site design, augmenting MicroStation s graphical capabilities with a set of dynamic and flexible site design tools. GEOPAK Site synchronizes design, analysis and conflict checking for all project phases: site, drainage, water and sewer and road design. Geared to handle the real-world iterative project process, GEOPAK Site lets you quickly explore a wealth of design scenarios. Special features handle any type of site object, from ponds to cul-de-sacs. Soil, rock or water volumes and material quantities are automatically calculated — enabling well-balanced, efficient planning that streamlines site development and construction. GEOPAK Site is used for a range of projects: commercial and manufacturing sites, urban complexes, subdivisions, parks and golf courses...
CircuitWorks for SolidWorks is a bi-directional IDF and PADS file interface for the SolidWorks 3D CAD system. CircuitWorks adds in to SolidWorks and allows it to read and write the industry standard IDF 2.0, 3.0 or 4.0 format files produced by Electrical CAD (ECAD) systems used for Printed Circuit Board (PCB) design. It can also read *.asc files from the Mentor PADS ECAD systemProduct:CircuitWorks 9 SP21 For SolidWorks Lanaguage:english Platform:Winxp/Win7 Size:10MB
::::::English Description:::::: With Abaqus/CAE you can quickly and efficiently create, edit, monitor, diagnose, and visualize advanced Abaqus analyses. The intuitive interface integrates modeling, analysis, job management, and results visualization in a consistent, easy-to-use environment that is simple to learn for new users yet highly productive for experienced users. Abaqus/CAE supports familiar interactive computer aided engineering concepts such as feature-based, parametric modeling, interactive and scripted operation, and GUI customization. Users can create geometry, import CAD models for meshing, or integrate geometry-based meshes that do not have associated CAD geometry. Interfaces for CATIA V5 and Pro/ENGINEER enable synchronization of CAD and CAE assemblies and enable rapid model updates with no loss of user-defined analysis features. The open customization toolset of ABAQUS/CAE provides...
::::::English Description:::::: PDS is a comprehensive, intelligent computer-aided design/engineering (CAD/CAE) application for plant design, construction, and operations. Production-driven, it helps EPCs and owner/operators deliver the best design possible – and do it more efficiently to reduce the total installed cost of the project. Due to its capability and commitment to the industry, many leading engineering firms and owner/operators have selected PDS as their corporate standard. PDS 2007 SmartPlant® Enabled (SE) Offers New Functionality PDS 2007 SE (version 8.0) offers a variety of new features. Because the product is SmartPlant-enabled, you can now export your PDS data into SmartPlant 3D using the PDS Export utility delivered with SmartPlant 3D version 6.0. You can also use the PDME Export command to export PDS for...
Additional Enhancements to Quartus II Software Version 8.0 * New tasks window: Provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library, including JTAG and SPI interfaces. * Enhanced FPGA I/O planning: Accelerates board development with added pin-swapping capabilities in the Pin Planner. * New IP advisor: Provides design-specific guidelines and recommendations for successful use of Altera’s PCI Express and DDR3 IP. * MegaCore® IP Library: Integrated in Quartus II software, making it easier for users to access Altera’s portfolio of IP cores. New additions with this release include PCI Express Gen2 hard IP, five new video and image...
nLint is a comprehensive HDL design rule checker fully integrated with the Verdi and Debussy debug systems. The Debussy system accelerates users understanding of complex designs to improve design, verification, and debug productivity. nLint adds the ability to fully analyze the HDL for syntax and semantic errors. nLint helps designers create correct HDL code by performing source code checks to ensure conformance with design rules such as synchronous design, clocking scheme, naming conventions, and testability. nLint helps uncovers errors early to reduce simulator, synthesizer, and ATPG run time and to reduce debug time. With nLint, users more easily create readable and maintainable code. They can enforce coding standards across design teams to achieve design re-use goals. nLint operates on design data...
::::::English Description:::::: A journey to the top of a mountain can take many different routes, but the reward is always the same: an amazing view. When youre scaling a mountain of data you want to see the most informative views – the ones that show the trends, the anomalies and the physics in your data. The next time you embark on an engineering or scientific project – be it simulation, analysis or experiment – count on Tecplot, the plotting and visualization software that helps present your work in its best light. And when you think of a new, better, or different way to present your data, Tecplot gives you full control over 2- and 3-D plot parameters. Conquer your mountains...
::::::English Description:::::: Major Benefits Cuts layout time in half while sustaining important aspects of handcrafted layout density Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout verification and correction without the need for data translation Supports latest process design rules to meet the physical implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM) Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users Device-level manipulation reduces tedious/error-prone layout creation and editing. Shape and Grid Based routers for both full custom and cell-based design applications Download foundry-certified Laker technology files to instantly use the plug-and-play Laker solution Schematic-Driven Layout Flow works efficiently with legacy and new designs Major...
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