Tags :HDL Designer Series

Mentor Graphics HDL Designer Series 2009.2 combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process. Key Benefits Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog Accelerates RTL Reuse Extensive design checking rules and rulesets Interactive HDL visualization and creation tools Automatic documentation features and reporting Intelligent debug and analysis Concurrent design entry and checking Design and Reuse Quickly assess reused code quality and increase design understanding Efficiently create RTL designs using text, tables, and graphics Interactively manage design flow and all project data Rapidly produce documentation...

::::::English Description:::::: HDL Designer delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. Comprehensive Design Creation & RTL Reuse Environment Any Silicon PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs Any Vendor Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry Any Language VHDL, Verilog, SystemVerilog, C/C++, PSL Any Flow Integrated with all leading Simulation, Emulation & Formal solutions Integrated with all commercial synthesis and P & R environments Optimizing RTL Reuse Practical reuse (online demo) (datasheet) Optimizing The Design Process Cut design time in half: Rapid design development process Team productivity: Team design flow and version management Tune your competitive edge: Flow management and...