Tags :Mentor Graphics Page 18

::::::English Description:::::: Our standards-based, integrated solution provides the necessary functionality to address the most complex issues faced by your design teams. The 6.4 series expands the advanced design and debug capabilities in ModelSim as well as delivering improved performance, capacity, support for new design and verification language features in SystemVerilog and numerous productivity and ease-of-use enhancements.  ModelSim SE (Special Edition) is our UNIX, Linux, and Windows-based simulation and debug environment, combining high performance with the most powerful and intuitive GUI in the industry. Features Multi-language, high performance simulation engine Verilog, VHDL, SystemVerilog Design Code Coverage SystemVerilog for Design Integrated debug JobSpy Regression Monitor Mixed HDL simulation option SystemC Option TCL/tk 32 and 64-bit platform support — Solaris, Linux, Windows product:Mentor...

::::::English Description::::::  Intuitive logic synthesis environment with advanced optimization techniques, award-winning timing analysis, and advanced inferencing technology. Precision RTL enables vendor-independent design, accelerates time to market, eliminates design defects and delivers superior quality of results (QoR).  product:Mentor Graphics Precision Synthesis 2007a.18 linux Lanaguage:english Platform:Winxp/Win7 Size:238MB

::::::English Description:::::: HDL Designer Linux delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. Comprehensive Design Creation & RTL Reuse Environment Any Silicon PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs Any Vendor Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry Any Language VHDL, Verilog, SystemVerilog, C/C++, PSL Any Flow Integrated with all leading Simulation, Emulation & Formal solutions Integrated with all commercial synthesis and P & R environments Optimizing RTL Reuse Practical reuse (online demo) (datasheet) Optimizing The Design Process Cut design time in half: Rapid design development process Team productivity: Team design flow and version management Tune your competitive edge: Flow management...

::::::English Description:::::: HDL Designer delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. Comprehensive Design Creation & RTL Reuse Environment Any Silicon PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs Any Vendor Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry Any Language VHDL, Verilog, SystemVerilog, C/C++, PSL Any Flow Integrated with all leading Simulation, Emulation & Formal solutions Integrated with all commercial synthesis and P & R environments Optimizing RTL Reuse Practical reuse (online demo) (datasheet) Optimizing The Design Process Cut design time in half: Rapid design development process Team productivity: Team design flow and version management Tune your competitive edge: Flow management and...

::::::English Description:::::: Mentor Graphics® Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the immediate availability of HyperLynx® 7.7, the latest version of its powerful and easy-to-use tool suite for pre- and post-layout signal integrity (SI) simulation and analysis. HyperLynx 7.7 includes significant productivity and technology enhancements targeted at classic high-speed bus technologies, as well as the rapidly emerging SERDES (SERialization/DE-Serialization) interconnect standards for connecting serial drivers and receivers. “I use HyperLynx because it is one of the few accurate circuit simulators with coupled lossy-line models and an integrated 2D field solver,” said Dr. Eric Bogatin, industry expert and author of Signal Integrity Simplified. “Plus, it is far and away the quickest...

::::::English Description:::::: Mentor Graphics I/O Designer provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB. Focused on optimizing system performance, designer productivity and reducing product manufacturing costs, I/O Designer eliminates the barriers between FPGA and PCB flows and design organizations.product:Mentor Graphics I/O Designer 7.2 Lanaguage:english Platform:Winxp/Win7 Size:102MB

ICX® and ICX Pro provide an intuitive user interface for engineers to explore signal integrity solutions in their high-speed designs. Engineers learning signal integrity are offered a concise view of how things work, while those more seasoned are able to investigate signal integrity effects in their designs in great detail. Components are modeled using industry standard IBIS models, with support for virtually all IC model types, while simulations are provided by our proven ICX simulation technology. With a library of default IBIS models provided, engineers can begin evaluating high-speed design solutions easily and quickly. The Tau® board-level symbolic timing analysis tool performs comprehensive worst-case timing analysis and verification on designs using an advanced symbolic timing methodology, eliminating false paths that...

::::::English Description:::::: Catapult is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Catapult is a high-level synthesis tool that uses industry-standard ANSI C++ to generate correct-by-construction, high-quality RTL 10-100x faster than other methods. Unlike traditional RTL design methodologies, Catapult enables the designer to pick the best architecture for given performance/area/power requirement and avoids the design errors introduced from hand coding the RTL description. product:Mentor Graphics Catapult Synthesis 2007b ESL Lanaguage:english Platform:Winxp/Win7 Size:110MB

Mentor Graphics TPD translators能够提供PCB 文件和 从Cadstar, OrCad, PCAD or Protel 的footprint libraries到PADS的转换。 ::::::English Description:::::: Mentor Graphics TPD translators Provides translation for PCB Layout files and footprint libraries from Cadstar, OrCad, PCAD or Protel to PADS Layout. product:Mentor Graphics TPD translators Lanaguage:english Platform:Winxp/Win7 Size:26MB

::::::English Description::::::  Mentor Graphics PADS Layout to Expedition Translators 2007  enable PADS files to Expedition files.product:Mentor.Graphics PEX 2007 Lanaguage:english Platform:Winxp/Win7 Size:25MB