Tags :RTL

Encounter RTL Compiler Global synthesis that enables concurrent optimization of timing, area, and power intentEncounter® RTL Compiler offers a unique set of patented global-focus algorithms that perform true top-down global RTL design synthesis to accelerate silicon realization. With concurrent multi-objective optimization (timing, area, and power intent) and support for advanced low-power design techniques, Encounter RTL Compiler reduces chip power consumption while meeting frequency goals. Encounter RTL Compiler performs multi-objective optimization that simultaneously considers timing, power, and area intent to create logic structures that converge on all these goals in a single pass. Features/Benefits A well-balanced logic structure isolates critical paths, reduces power, area, and congestion in off-critical logic, and enables faster timing closure and design convergence through placement and routing...

Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics’ FPGA Flow– the industry’s most comprehensive FPGA vendor independent solution.Physical Synthesis Average performance improvement of 10%Support for Actel, Altera, Lattice and XilinxMil-Aero, Safety-Critical, & DO-254 Repeatability of resultsSynthesis for design assuranceIntegration with Mentor tools for DO-254Low Power Synthesis Optimizations to reduce dynamic powerMulti-vendor supportIncremental Synthesis Fully automatic incremental synthesisPartition-based incremental synthesisReduces runtime and preserves QoRIntegrated with incremental place-and-routePrecise-IP™ Generate building block IP for any deviceLeverage 3rd party IP validated for PrecisionPrecise-Encrypt Vendor independent HDL encryptionBased on IEEE P1735 draftInteroperable with ModelSim & QuestaIntegration with Mentor Tools Design reuse with HDL Designer™Equivalence checking with FormalPro™Requirements tracking with ReqTracer™FPGA-PCB co-design with I/O DesignerResource Manager Graphical analysis of embedded...

Precision RTL Plus Precision RTL Plus is Mentor Graphics’ flagship FPGA synthesis solution offering breakthrough advantages for commercial applications and for mil-aero and safety-critical systems. Precision RTL Plus offers an improved way of designing FPGAs and increasing designer productivity. Through its advanced synthesis technologies and integration within Mentor’s FPGA flow, it provides several unique features that enable every designer to reach timing closure faster, to minimize the impact of design changes, and to address application-specific requirements.Key Features & BenefitsPhysical Synthesis Average performance improvement of 10% Support for Actel, Altera, Lattice and Xilinx Mil-Aero, Safety-Critical, & DO-254 Repeatability of results Synthesis for design assurance Integration with Mentor tools for DO-254 Low Power Synthesis Optimizations to reduce dynamic power Multi-vendor support Incremental...

Cadence Encounter RTL Compiler 9.1 Linux allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and power. To maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power. Encounter RTL Compiler, a key component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon. Features/Benefits A well-balanced logic structure isolates critical paths and reduces power,...