Tags :SPICE

::::::English Description:::::: While today’s chip designs demand increasing speed and performance, designers are also faced with the challenge of verifying their chips at both analog and logic levels expediently due to shortened product life cycle. Full-chip simulations require prudent setup and tend to create large amount of simulation data to review. Moreover, typical design process involves iterative simulations – a time consuming process. SPICE Explorer is developed to address the newly arisen necessity for an effective transistor-level debugging environment. The tool is built upon netlist-driven debugging and visualization modules, and WaveView Analyzer with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost. Features Screens netlist for issues from...