Tags :Synopsys Design Compiler 2019.03 SP3

Synopsys Design Compiler 2019.03 SP3 This course covers the RTL synthesis flow: Using Design Compiler in Topographical mode to synthesize a block-level RTL design to generate a gate-level netlist with acceptable post-placement timing and congestion. You will learn how to: Read in hierarchical block-level RTL designs; Load libraries, technology data and floorplan constraints; Apply and verify constraints for complex design timing; Use timing- and congestion-focused DC Ultra and DC Graphical optimization features, which includes the SPG flow, to achieve post-placement timing closure and acceptable congestion; Analyze synthesis results for timing and congestion; Generate output data required by physical design or layout tools. The course includes labs to reinforce and practice key topics discussed in lecture. Optionally, you will verify the...