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::::::English Description:::::: The Formality® Equivalence Checker uses formal techniques to prove or disprove equivalence between two versions of the same design. Equivalence checking is a type of static analysis that verifies large designs both quickly and completely without the use of test vectors. The high performance and reduced risk of static analysis has led to the rapid adoption of equivalence checking within leading verification flows, making it a must for all competitive design processes.  Key Benefits共享软件资源网 Exhaustive verification, without test vectors, in a fraction of the time consumed by traditional dynamic techniques Proves functional correctness of register retiming, complex datapath, ECO, and low power implementations–from within a single product Reduces manual setup with verified automated setup guidance Verifies full-custom and...

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

Simulates and analyzes systems, sub-systems and components (hydraulic, electronic, mechanical, thermal, etc.) under a variety of different operational and environmental conditions * Optimize system for performance, reliability, and cost * Reduce effects of variation * Bound worst case behavior * Repeatable processes – create 10,000s of virtual prototypes * Increase reliability for mechatronic systems, PCBs & wire harnesses * Implement Robust Design analyses such as stress, sensitivity, Monte Carlo, etc. * Quickly create a virtual system design * Reduce the need for physical prototypes * Increase model portability with language standards VHDL-AMS & MAST * Ensure accuracy by accessing a library of 30,000+ models * Create models quickly with model characterization tools * Protect intellectual property with model encryption *...

The Milkyway™ Database provides the unifying design storage for Synopsys?Galaxy™ Design Platform. The production-proven, widely used Milkyway database provides persistent data storage that links Galaxy platform tools together thereby eliminating the need for large, intermediate exchange files and preventing design intent loss through mismatched syntax of exchange formats. Milkyway is proven on well over 10,000 tape-outs including the latest 90 and 65 nanometer technology designs. Designed to be extensible, Milkyway is continuously augmented with new capabilities such as those required for signal integrity, power reduction, and yield enhancement. The Milkyway database C-API was opened for customer interfacing in 1998 and is available to 3rd parties at no charge through Synopsys MAP-in program.   Key Features and Benefits Production-proven database for...

::::English Description:::::: Timing closure in today advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers...

High-Level Algorithm Implementation for FPGAs and ASICs The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.product:Synopsys Synthesis Tools 2008.09 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:277MB

* Rapidly create and verify technology independent DSP models that are fully portable across vendor and device technologies. * Unique Synplify DSP synthesis engine automatically creates optimized algorithm RTL architectures from your DSP model. * Powerful DSP synthesis optimizations enable exploration of speed/area/device technology tradeoffs without changing your DSP model or verification. * Comprehensive DSP library with full multi-rate support and advanced fixed-pint quantization analysis. * M-Control feature enables use of M-language for concise expression of complex state machine and control logic functionality. * Vector support enables concise expression of parallel and multi-channel algorithms common in wireless and video applications.product:Synopsys Synthesis Tools 2008.09 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:268MB

ynopsys, Inc. is the solutions leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ . NOTE: Synopsys is a registered trademark and Magellan is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their...

The installation instructions in this document are the most up-to-dateavailable at the time of production. However, changes might have occurred.For the latest installation information, see the product release notes ordocumentation.This document provides instructions for the UNIX, Linux, and Windowsplatforms. The document includes the following sections:Preparing for InstallationInstalling SpiceExplorer and WaveView Analyzer (UNIX and Windows)Invoking SpiceExplorer and WaveView Analyzer on WindowsInstalling the SX-CDS Link PackageInstalling the SX-DAIC Link PackageInstalling the SX-VSDE Link PackageViewing and Printing SpiceExplorer and WaveView AnalyzerDocumentation in Portable Document Format (PDF)Troubleshooting SpiceExplorer and WaveView Analyzer Installation onSolaris PlatformsUninstalling SpiceExplorer and WaveView AnalyzerCustomer Supportproduct:Synopsys SpiceExplorer 2008.03 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:54MB