Tags :Synopsys Page 11

Synopsys Analysis and Debug products provide a unique approach to transistor-level verification that enables engineers to efficiently analyze and debug complex AMS systems-on-chips (SoCs). CustomExplorer addresses the need for an effective transistor-level debugging environment. The tools provide a netlist-driven debugging and visualization modules, and Custom WaveView with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.product:Synopsys SpiceExplorer 2008.09 Win Lanaguage:english Platform:Winxp/Win7 Size:9MB

Synopsys\’ Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer\’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits * Finds complex bugs, such as those associated with multiple clock domains using static analysis * Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro *...

OverviewWith process geometries reaching90-nanometers (nm) and below, thereare many nanometer effects that canimpact timing. Accurate analysis ofthese effects is required to identify realtiming issues.Synopsys’ NanoTime tool is thenext-generation transistor-levelstatic timing analysis solution thataddresses the emerging challengesin signal integrity (SI) analysisassociated with custom designs.NanoTime offers concurrent timingand SI analysis, accuracy withinfive percent of HSPICE®, and theperformance required to analyzecomplex transistor circuits overnight.Its seamless integration with Synopsys’PrimeTime® product enables full-chipanalysis of designs that includes bothgate- and transistor-level blocks.NanoTime is a key component of theSynopsys custom design verificationsolution that includes CustomSim®and HSPICE for circuit simulationand ESP-CV for symbolic simulation.product:Synopsys Nanotime 2007.12 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:81MB

The Milkyway™ Database provides the unifying design storage for Synopsys’ Galaxy™ Design Platform. The production-proven, widely used Milkyway database provides persistent data storage that links Galaxy platform tools together thereby eliminating the need for large, intermediate exchange files and preventing design intent loss through mismatched syntax of exchange formats. Milkyway is proven on well over 10,000 tape-outs including the latest 90 and 65 nanometer technology designs. Designed to be extensible, Milkyway is continuously augmented with new capabilities such as those required for signal integrity, power reduction, and yield enhancement. The Milkyway database C-API was opened for customer interfacing in 1998 and is available to 3rd parties at no charge through Synopsys\’ MAP-in program. Key Features and Benefits * Production-proven database...

Synplicity’s Synplify Premier Linux software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates...

TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It\’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys\’ patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compact tests for even the most complex designs. PDFDownload Datasheet Key Benefits * Increases product quality with power-aware test patterns for high defect detection * Reduces testing costs through the use of advanced pattern compaction techniques * Increases designer productivity by leveraging integration with Synopsys DFTMAX compression * Creates tests for complex and multi-million gate designs Features * Extremely high capacity and performance * Multicore support for accelerated run...

Current ActivitiesAs an extension of the worldwide VERA R&D team, the Synopsys India VERA group is responsible for the development of standalone VERA tools and enhancements to the VERA language. It is also involved in various VERA integration projects including those with third party tools. The team\’s mission is centered on making ongoing key R&D contributions to the VERA product. Job ResponsibilitiesThe VERA R&D team works on technologies and products in the area of functional verification. Specific projects include design and development in: compilers, data structures, algorithms in support of the VERA runtime library, interfaces between VERA and 3rd party simulation tools, and GUIs. Job RequirementsAn ideal candidate desirous of working in this area should have experience in developing and...

The third product in the process-aware design-for-manufacturing (PA-DFM) family is Fammos; the first special-purpose TCAD PA-DFM tool that analyzes stress evolution for the entire fabrication process of interconnects. Fammos performs 3D backend process simulations using design database and process recipes. With specialized algorithms for fast 3D structure construction, mesh generation, and equation solving, Fammos predicts interconnect stress distributions from multiple stress sources and accounts for proximity effects. Combining the best-in-class capabilities from Synopsys, Fammos is capable of detecting stress hot spots that are susceptible to debonding, voiding and cracking. It employs a set of physics-based models to evaluate reliability failures. Using the Sentaurus Workbench user interface, Fammos will facilitate technology explorations with parameterized input files and scheduled run splits. Benefits...

Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus Process is a new-generation process simulator for addressing the challenges found in current and future process technologies. Equipped with a set of advanced process models, which include default parameters calibrated with data from equipment vendors, Sentaurus Process provides a predictive framework for simulating a broad range of technologies from nanoscale CMOS to large-scale high-voltage power devices. Sentaurus Process is part of the comprehensive Synopsys suite of core TCAD products for multidimensional process, device, and system...

::::::English Description::::::  HSPICE is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and comprehensive circuit simulator. Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield of their designs. As board and package speeds increase, designers need to employ increasingly accurate signal integrity analysis. SolutionHSPICE <!– Key Benefits –> Accuracy Gold standard for accurate circuit simulation. Extensive model support of the most accurate and expansive set of industry-standard and...