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ynopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...

::::::English Description:::::: HSIMplusHSIMplus™ 2007.03 Linux is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete solution for analysis of the effects that dominate performance and reliability in silicon at 90nm and 65nm process nodes. HSIM® delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques: Hierarchical Storage and Isomorphic Matching   Hierarchical StorageTraditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver...

:::::: HSIMplusHSIMplus™ 2007.03 is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete solution for analysis of the effects that dominate performance and reliability in silicon at 90nm and 65nm process nodes. HSIM® delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques: Hierarchical Storage and Isomorphic Matching   Hierarchical StorageTraditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver in HSIM...

。Complete and accurate cell characterization is essential for automated implementation and verification of complex system-on-chips (SoC). Capturing sufficiently accurate timing, power and signal integrity information, as well as operating condition variability for 90-nm and 65-nm technologies requires major additions to the technology information developed for previous technologies. Synopsys?NanoChar characterization system is a complete, automated, characterization solution for standard cells and other macrocells that delivers the accuracy and capabilities required for 90-nm and below process geometries.Working in conjunction with Synopsys?highly-accurate HSPICE circuit simulator, NanoChar characterization system derives critical timing, power, and signal integrity data to create open, industry-standard Liberty (.lib) and Verilog (.v) files for use by all Synopsys tools as well as other EDA tools. The NanoChar characterization system lowers...

Synopsys Saberproduct:Synopsys Saber 2007.03 linux Lanaguage:english Platform:Winxp/Win7 Size:392MB

::::::English Description:::::: Synopsys’ Leda® 2007.03 is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda抯 pre-packaged rules greatly enhance a designer’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality.   Key Benefits Finds complex bugs, such as those associated with multiple clock domains using static analysis Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro...

The DesignWare Library provides a comprehensive portfolio of synthesizable and verification IP including an AMBA-based on-chip bus solution, memory IP, popular processor cores, bus and I/O standards, and performance enhancing datapath IP elements. The following product documentation is for the DesignWare Library\’s synthesizable and verification IP components. You can access product documentation for the DesignWare digital and mixed-signal IP cores using the “Search for IP” box in the upper right hand corner of this page.product:Synopsys DesignWare.vip Smartmodels 2005.09 Lanaguage:english Platform:Winxp/Win7 Size:101MB

Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced the availability of advanced device parameter measurement functionality in its Hercules(TM) Physical Verification Suite (PVS). Developed to support the latest release of 65-nanometer (nm) design kits from IBM (NYSE: IBM), this new functionality enables IBM foundry customers using the Hercules layout versus schematic (LVS) rule files in the kit to easily and accurately correlate device behavior to the IBM process. These IBM foundry customers also have access to the latest Hercules design rule checking (DRC) as part of the 65 nm design kit release. These files are qualified for accuracy and optimized for performance. “We have been supporting Synopsys Hercules PVS for over a decade,” said Dave Harame, director...

>::::::English Description:::::: Raphael is the gold standard, 2D and 3D resistance, capacitance, and inductance extraction tool for optimizing multi-level interconnect structures and on-chip parasitics in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide. Benefits Analyze complex on-chip interconnect structures and the influence of process variation Create a parasitic database for both foundries and designers to study the effect of design rule change Generate accurate capacitance rules for layout parameter extraction (LPE) tools product:Synopsys Raphael 2006.12 Linux Lanaguage:english Platform:Winxp/Win7 Size:36MB

FEATURED TECHNOLOGY CustomSim Circuit SimulationUnified AMS verification technologies deliver 4x performance improvement VCS Multicore Technology2x verification speed-up on complex designs Lynx Design SystemThe Lynx Design System is a highly automated, production-ready, chip implementation platform. Power-Aware TestBreakthrough technology in DFT MAX compression and TetraMAX ATPG. SuperSpeed USB 3.0Learn about USB 2.0 vs. 3.0 and how to evaluate a USB IP solution.product:Synopsys Circuit Explorer 2006.03 Linux Lanaguage:english Platform:Winxp/Win7 Size:62MB