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Synopsys Synplify vJ-2015.03 SP1 Synplify Pro® FPGA synthesis software, part of the Synopsys FPGA design solution, is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Lattice Semiconductor, Microsemi (formerly Actel), SiliconBlue and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use...

Synopsys.FineSim.2015.06.LinuxMulti-Core/Multi-Machine Enabled Full-Chip Circuit-Level Simulation OverviewFineSim™ is a high-performance circuit simulator with built-in full SPICE and FastSPICE simulation engines. FineSim\’s unique multi-core/multi-machine simulation capability allows users to drastically improve simulation performance and capacity. FineSim is well-suited for simulation of large, complex analog circuits, as well as DRAM/SRAM/Flash memory design. IntroductionTypically, analog and digital blocks are verified independently with different simulation technology that varies in accuracy. When analog and digital blocks are combined in one simulation, due to capacity limitations of traditional simulators, verifying them together usually requires some additional modeling techniques that only approximate circuit behavior. In some cases, this can introduce false design errors causing engineers to spend a significant amount of time searching for the root cause. As...

Functional Verification Choice of Leading SoC Design Teams OverviewIndustry-leading designers of today’s most advanced designs rely on the Synopsys VCS® functional verification solution for their verification environments. In fact, a high majority of designs at 32nm and below are verified with VCS. Used by a majority of the world’s top 20 semiconductor companies as their primary verification solution, VCS provides high-performance simulation engines, constraint solver engines, Native Testbench (NTB) support, broad SystemVerilog support, verification planning, coverage analysis and closure, an integrated debug environment, and offers X-propagation support (VCS Xprop) for X-related simulation and debug. VCS has continually pioneered numerous industry-first innovations, and is now poised to meet the challenges and complexity of today’s SoCs. With features such as such as...

The Gold Standard for Accurate Circuit Simulation HSPICE is the industry\’s \”gold standard\” for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry\’s most trusted and comprehensive circuit simulator. For on chip simulation: Analog designs, RF design, custom digital design, standard cell design and characterization, memory design and characterization, and device model development. For off chip signal integrity simulation: Silicon to package to board to backplane analysis and simulation Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield...

Golden Signoff Solution The Synopsys PrimeTime suite provides a single, golden, trusted signoff solution for timing, signal integrity, power and variation-aware analysis. It delivers HSPICE® accurate signoff analysis that helps pinpoint problems prior to tapeout thereby reducing risk, ensuring design integrity, and lowering the cost of design. This industry gold-standard improves your team’s productivity by delivering fast turnaround to shave precious time from development schedules for large and small designs while ensuring first-pass silicon success through greater predictability and the highest accuracy. he Synopsys PrimeTime suite includes PrimeTime, PrimeTime SI, PrimeTime ADV, PrimeTime GCA, PrimeTime PX and PrimeTime VX. Anchored by the most trusted and advanced static timing signoff solution for gate-level designs, the PrimeTime suite offers comprehensive signal integrity...

Synopsys\’ IC Compiler II Accelerates Silicon Validation of Imagination\’s Ground-breaking PowerVR® Ray Tracing IP Imagination\’s IMGworks Platform IP Group Leverages Long Standing Collaboration with Synopsys to Make Full Use of IC Compiler II\’s Advanced CapabilitiesHighlights: IC Compiler II\’s game-changing capacity, turnaround time and productivity help shrink Imagination\’s IMGworks Platform IP Group schedules from concept to siliconMutual customers to benefit from Imagination\’s fully validated IC Compiler II reference flows in future DOK\’s (Design Optimization Kits)Up to 10X improvement in design planning throughput (compared to previous production environment) and accelerated block implementation help deliver best-in-class SoC implementation flowproduct:Synopsys IC Compiler II 2015.06 Lanaguage:english Platform:Linux/Macosx Size:1DVD

Complete Transistor-Level Analysis and Debugging Environment OverviewCustomExplorer™ provides a complete transistor-level analysis and debugging environment for pre-processing and post-processing SPICE and FastSPICE simulations. CustomExplorer is integrated with Synopsys’ HSPICE® and CustomSim™ to streamline the debugging and analysis process for SPICE and FastSPICE simulation and increase design productivity. The combination of CustomExplorer with CustomSim and HSPICE simulators provides design teams with a high-performance, productive simulation debug and analysis environment for complex SoC design. Download Datasheet IntroductionCustomExplorer™ is a netlist-based debugging environment for SPICE and FastSPICE simulators such as HSPICE and CustomSim. CustomExplorer is also tightly integrated with Custom WaveView™, enabling waveform cross-probing. Together, these tools aid designers in rapidly performing customized advanced analyses in a highly-productive design debugging and waveform analysis...

Saber is a proven platform for modeling and simulating physical systems, enabling full-system virtual prototyping for applications in analog/power electronics, electric power generation/conversion/distribution and mechatronics. Decades of industry success and innovation have earned Saber a reputation as the solution of choice for design validation and optimization for automotive, aerospace, industrial power and energy systems. Focus: Virtualize power electronic and mechatronic systems to optimize performance and reliabilityAccelerate the electrification of automotive, aerospace and industrial systemsIncrease hardware quality and reduce prototyping iterationsConnect the physical system to the rest of the electronics and software designSaberRD: Integrated Environment for Physical Modeling and SimulationEasy to use—Windows-based IDENovice accessibility—Expert flexibilityProven technologyDownload Demo/Student versionKey benefits and design goals:Verify behavior of multi-domain physical systems (electrical, thermal, mechanical, magnetic,...

Premier graphical waveform analyzer OverviewToday\’s complex integrated circuit (IC) designs generate a vast amount of simulation data. CosmosScope™ turns that mountain of data into useful information. With powerful analysis and measurement capabilities, patented waveform-calculator technology, and scripting language based on the industry standard Tcl/Tk, CosmosScope offers unparalleled capability and flexibility to analyze design performance and ensure design quality. CosmosScope supports all Synopsys simulators: HSPICE®, NanoSim™, Saber® and SaberHDL. CosmosScope benefits Supports all Synopsys simulation products with a single viewer including HSPICE, NanoSim Saber, and SaberHDL Provides powerful Tcl/Tk-based scripting language for easy customization Performs post-processing of analog and digital simulation results Automatically annotates graphs with design information using true WYSIWYG graphics, including arrows, shapes and text Annotates graphs with 50...

Accelerate Design Innovation with Design Compiler® Synopsys\’ Design Compiler® family of products in the Galaxy™ Implementation Platform maximizes your productivity with its complete solution for RTL synthesis and test, Design Compiler Graphical, uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best in class quality of results for your most challenging designs at all process nodes. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. Design Compiler Graphical also produces physical guidance to IC Compiler that tightens timing and area correlation and speeds-up placement runtimes. Design Compiler Graphical is built upon DC Ultra™ synthesis that concurrently optimizes for timing, area, power and test and...