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Formality and Formality Ultra Verifies the toughest designs synthesized with DC OverviewFormality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all DC Ultra and Design Compiler Graphical optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality Ultra adds innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs with minimal impact to...

TetraMAX ATPG Automatic Test Pattern Generation OverviewTetraMAX® ATPG automatically generates high quality manufacturing test patterns. It’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys’ patented DFTMAX™ and DFTMAX Ultra, the leading test synthesis tools. The unparalleled ease-of- use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compressed test patterns for even the most complex designs. Download Datasheet Key Benefits Improves product quality with comprehensive fault model support and power-aware test patterns Increases designer productivity by leveraging integration with Synopsys test compression tools Generates test patterns for even the largest and most complex SoCs Enables faster yield ramp by quickly isolating defect locations Features Extremely high capacity...

Comprehensive Place and Route System OverviewIC Compiler is the leading place and route system. A single, convergent, chip-level physical implementation tool, it includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs at all process nodes. IC Compiler is the industry leading place-and-route system for established and emerging process technology node designs. Multicore support throughout the flow delivers improved productivity. New technologies, like concurrent clock and data (CCD) with clock concurrent optimization, PrimeTime physically-aware engineering change order (PT-ECO) guidance with minimum physical impact implementation, and golden unified power format (IEEE 1801 UPF), enable designers to handle gigascale design complexity and meet tight project schedules. IC...

TetraMAX ATPG Automatic Test Pattern Generation OverviewTetraMAX® ATPG automatically generates high quality manufacturing test patterns. It’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys’ patented DFTMAX™ and DFTMAX Ultra, the leading test synthesis tools. The unparalleled ease-of- use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compressed test patterns for even the most complex designs. Key Benefits Improves product quality with comprehensive fault model support and power-aware test patterns Increases designer productivity by leveraging integration with Synopsys test compression tools Generates test patterns for even the largest and most complex SoCs Enables faster yield ramp by quickly isolating defect locations Features Extremely high capacity and performance...

Synopsys coreToolsIP Based Design and VerificationOverviewThe Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools foruse in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gainswhen using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the riskconfiguration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction inSoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge and design intent of the IPand provide graphical or command based configuration menus for the...

Synplify Pro® FPGA synthesis software, part of the Synopsys FPGA design solution, is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Lattice Semiconductor, Microsemi (formerly Actel), SiliconBlue and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the...

OverviewIC Compiler is an integral part of the Synopsys Galaxy™ Implementation Platform that delivers a comprehensive design solution, including synthesis, physical implementation, low-power design, and design for manufacturability. IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, manufacturability, and low-power capabilities that enable designers to implement today’s high-performance, complex designs on schedule. Download Datasheet IC Compiler is a comprehensive place-and-route system; it provides best QoR in timing, area, power, signal integrity, routability, out-of the-box results and faster design closure. Multicore support throughout the flow delivers improved productivity. New technologies enable designers to handle gigascale, complex designs and meet tight project schedules. IC Compiler is tightly...

Synplify Pro® FPGA synthesis software, part of the Synopsys FPGA design solution, is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Lattice Semiconductor, Microsemi (formerly Actel), SiliconBlue and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the...

OverviewThis course introduces concepts on full-speed hardware debugging using the Identify® toolset which provides an “embedded HDL analyzer” with debug access at the RTL level similar to an RTL simulator. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect. ObjectivesThe course focuses on understanding concepts on instrumenting the design and using the Identify® product to successfully verify the functionality of hardware. Audience ProfileDesigners who wish to move away from basic logic analyzer capabilities inside an FPGA and perform real-world full-speed verification of their hardware. PrerequisitesKnowledge of logic synthesis and FPGA technologies. Course Outline Identify Instrumentor IICE™ Identify...

Industry-leading designers of today’s most advanced designs rely on the Synopsys VCS© functional verification solution for their verification environments. In fact, 90% of designs at 32nm and below are verified with VCS. Used by a majority of the world’s top 20 semiconductor companies as their primary verification solution,VCS provides the high performance simulation engines, constraint solver engines, Native Testbench (NTB) support, broad SystemVerilog support, verification planning, coverage analysis and closure, and an integrated debug environment. VCS has continually pioneered numerous industry-first innovations, and is now poised to meet the challenges and complexity of today’s SoCs. With features such as constrained random testbench, SoC optimized compile flow, coverage, and assertions, VCS has the flexibility and capabilities that are critical for today’s...