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OverviewFormality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time. PDFDownload Datasheet Key benefits Perfect companion to DC Ultra – supports all...

PrimeTime® static timing analysis (STA) suite includes two key improvements that deliver a dramatic boost to designer productivity. This latest release includes a flexible multicore processing technology that makes more effective use of both single-core and multicore CPUs across today’s compute server farms, better harnessing their compute potential. This release also introduces new runtime optimizations, allowing design engineers to run faster full timing and signal integrity (SI) analysis on their large designs early in the implementation process, thus reducing costly design closure iterations. These improvements work in concert to deliver up to 2X faster runtime and have been confirmed on a suite of leading semiconductor companies’ designs ranging in size from one million to 50 million instances.product:SynopSys PrimeTime v2012.12 Lanaguage:english...

The Gold Standard for Accurate Circuit Simulation HSPICE is the industry\’s \”gold standard\” for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry\’s most trusted and comprehensive circuit simulator. PDFHSPICE Datasheet For on chip simulation: Analog designs, RF design, custom digital design, standard cell design and characterization, memory design and characterization, and device model development. For off chip signal integrity simulation: Silicon to package to board to backplane analysis and simulation Design ChallengesAs IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality,...

Highest-throughput mixed-signal simulation with CustomSim and VCS The majority of today’s designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed I/O devices. To complete verification of SoCs that contain a combination of RTL and synthesized logic, along with custom digital and analog circuits; Discovery AMS analog/digital co-simulation provides a direct kernel integration between Synopsys CustomSim, VCS and VCS-MX. Overview OverviewDiscovery AMS provides a comprehensive environment that enables verification of full-chip mixed-signal designs with built-in support for Verilog-AMS language defined by the Accellera 2.0 standard. It provides a unique combination of accuracy, performance and capacity with the flexibility of simulating design abstractions...

HSPICE 2011.09 – Major Enhancements in September 2011 Release HSPICE for Analog HSPICE Precision Parallel technology extended beyond transient analysis to support transient noise, Monte Carlo, IBIS, and MOS reliability analysis (MOSRA) HPP technology now delivers 10X scaling on 16 cores Distributed Processing Distributed processing now supports DC Monte Carlo analysis Signal Integrity Parallel S-parameter evaluation improves HPP scaling on high-speed circuits W-element field solver now supports multi-threading, delivers 5X speed-up on 8 cores, enables faster analysis of complex traces at more frequency points Multiple edges support in StatEye analysis increases eye diagram accuracy for strongly nonlinear buffers New Model Support BSIM 4.7 BSIMSOI 4.4 HiCUM Level 0 1.3 HiCUM Level 2 2.3 HiSiM 2.5.1 HiSIM_HV 1.2.1, 1.1.2 and 2.0.0...

CustomExplorer™ and Custom WaveView™ form a comprehensive transistor-level debugging environment for analog, mixed-signal and SoC designs. CustomExplorer provides a host of tools for navigating transistor-level designs and verifying simulation results. Download Datasheet IntroductionCustomExplorer is tightly integrated with Custom WaveView, enabling customizable waveform analysis. Custom WaveView provides powerful tools for displaying waveforms, performing calculations and making measurements (see Figure 1). Together, these tools aid designers in rapidly performing customized advanced analyses in a highly-productive design debugging and waveform analysis environment. CustomExplorer Design BrowsersThe Design Browsers allow quick access to the most complex hierarchy design data. After loading a netlist or simulation results, the user can probe the design’s hierarchy by expanding the Lint, File, Deck, Flat or Output View tabs. These...

NanoSim™ is the cornerstone of Synopsys’ comprehensive mixed-signal verification solution, Discovery AMS. NanoSim is an advanced transistor-level circuit simulation and analysis tool for analog, digital and mixed-signal design verification. It is a robust and easy to use solution, with very high simulation throughput and capacity for multi-million transistor SoC’s and accuracy for designs at 90 nanometer and below. Key Benefits * Provides high accuracy for designs at 90 nanometer and below * Simulation speeds up to orders of magnitude faster than SPICE * Capacity to simulate large memory and SoC designs, e.g. 512 Mb DRAM with 1 Billion elements * Provides flexibility to trade-off accuracy versus performance * Seamless integration with parasitic extraction tool, Star-RCXT for efficient post-layout simulation *...

The Synplify solution is a high-performance, sophisticated logic synthesis engine that utilizes proprietary Behavior Extracting Synthesis Technology (B.E.S.T.) to deliver fast, highly efficient FPGA and CPLD designs. The Synplify product takes Verilog and VHDL Hardware Description Languages as input and outputs an optimized netlist in most popular FPGA vendor formats.New Release Also Delivers DesignWare Library IP Support for Production FPGA Designs 2010.09 Release Highlights: — Up to 4X synthesis runtime improvement — New global placer for quality of results improvements on existing designs — New team-design feature for concurrent design development — New support for DesignWare Library datapath and building block components for FPGA Implementation and ASIC Prototyping MOUNTAIN VIEW, Calif., Sept. 27 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a...

Process and Device Simulation Tools Technology Computer-Aided Design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and devices. Synopsys TCAD offers a comprehensive suite of products that includes industry leading process and device simulation tools, as well as a powerful GUI-driven simulation environment for managing simulation tasks and analyzing simulation results. The TCAD process and device simulation tools support a broad range of applications such as CMOS, power, memory, image sensors, solar cells, and analog/RF devices. In addition, Synopsys TCAD provides tools for interconnect modeling and extraction, providing critical parasitic information for optimizing chip performance.Technology Computer-Aided Design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and...

Saber is a multi-domain modeling and simulation environment that enables full-system virtual prototyping for applications in analog/power electronics, electric power generation/conversion/distribution and mechatronics. Decades of industry success and innovation have earned Saber a reputation as the solution of choice for design validation and optimization for automotive, aerospace and industrial systems. SaberRD: Desktop Environment for Power Electronic Design * Introduced in 2010 * Easy to use—Windows-based IDE * Novice accessibility—Expert flexibility * Proven technology * Demo/Student version Focus: Manage power electronic and mechatronic complexity by accelerating Robust Design via simulation * Automotive (mid-class car) — 50+ microprocessors, 100+ sensors, 30+ electrical subsystems * Aerospace (A380) — 530km of wires, 100,000 cable sections, 40,300 connectors * Solar — power electronics, control algorithms,...