Synopsys SOLD 2009.06帮助文档.这主要是galaxy_docs_2009.06. The Synopsys Online Documentation collection (SOLD) is for Synopsys Implementation Group products only. such as Design Compiler, IC Compiler, Formality, Power products, PrimeTime, Star-RCXT, and TetraMax.product:Synopsys SOLD 2009.06 Lanaguage:english Platform:Winxp/Win7 Size:3.68G
VCS® is the industry?s most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. The VCS solution?s advanced bug-finding technologies include full-featured Native Testbench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, the VCS Verification Library provides verification IP for today?s most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, the VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. The VCS solution?s powerful debug and visualization environment minimizes the turnaround time to find and fix design...
VCS MX uses the Synopsys Installer tool, which allows you to use agraphical user interface (GUI) or a text script. For information aboutdownloading Synopsys Installer and VCS MX, see “Downloading theSoftware” in Installing Synopsys ToolsTo install VCS MX by EST or from the CD, follow the proceduresdescribed in Installing Synopsys ToolsExample 1-1 in Installing Synopsys Tools shows a Synopsys mediainstallation script for the synthesis tools. VCS MX is installed in a similarmanner.VCS MX is a stand-alone product and cannot be installed over an existingSynopsys product, including a prior version of VCS MX. You must createa new directory for VCS MX.Follow these steps.1. Set the VCS_HOME environment variable in the shell that you are usingin which the root_directory argument is the...
The ChallengeAccurate transistor-level analysis of crosstalk-delayAs designs go down to 90-nm and below, crosstalk-delay becomes more than 25%of total delay. Prior solutions including traditional static timing analysis with optional3rd party crosstalk delay analysis do not provide the accuracy and productivity thatis required. Concurrent timing and SI is a must to achieve silicon success.Full chip timing verificationTransistor- and gate-level static timing analysis need to work together to achievefull chip timing verification (i.e) a seamless and accurate timing analysis flowfrom custom design to gate-level with PrimeTime is required. To achieve higherproductivity, NanoTime has the same commands as PrimeTime whenever theyare applicable.Concurrent timing and signal-integrity (SI) analysis provides higherpredictability and better productivityover existing solutions. NanoTimeoffers integrated timing and crosstalk-delay analysis to achieve higher...
Installing TetraMAXThis section describes Synopsys license key requirements and the two types of installationfor TetraMAX ATPG and TetraMAX IddQTest, version B-2008.09.You can install TetraMAX as a stand-alone product or as an overlay product.• Stand-alone (txs)Install TetraMAX stand-alone in its own directory. The product ID for the stand-aloneversion is txs.• Overlay (tx)Install TetraMAX overlay in the same directory as the appropriate release of the synthesistools. See “Overlay Installation” The product ID for the overlay version is tx.Note:If you are going to install TetraMAX IddQTEST, you must install it first (see “OptionalInstallation of IddQTest”), then install TetraMAX ATPG as an overlay to the synthesis tools.License Key RequirementsTetraMAX version B-2008.09 uses the Synopsys Common Licensing (SCL) system. Forinformation about downloading SCL, installing SCL,...
::::::English Description:::::: Timing closure in today抯 advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure. The PrimeTime STA SolutionThe Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry抯 de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform. With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It...
OVAs provide language capabilities to build and reuse libraries of pre-built assertions. This macro capabilityprovides a mechanism to build a reusable library of assertions, which can be shared within groups or amongthe OpenVera community. With a library of assertions, designers will be able to reuse the prior specificationsand raise the level of abstraction of the specification.OVAs are part of the OpenVera open source standard. The open source model has been demonstrated toprovide a path for fast time to market with innovation and contribution from multiple sources.OVAs FeaturesOVAs are declarative with semantics that are formally based on the theories of regular expression and lineartemporal logic. These two theories provide a powerful combination for expressing common hardware activities,such as sequencing, invariants and...
Recent collaboration between UMC and Synopsys has resulted in a complete RTL-to-GDSII reference design flow, which now includes critical design for manufacturing features for UMC抯 90nm process. Suzanna Chang, Senior Director of Marketing for UMC, and Paul Lai, Group Manager of Strategic Alliances, Synopsys, explain how the use of this flow can help designers reduce design risk and speed time to results. UMC\’s Design for Manufacturing (DFM) efforts supplement the basic design work that is performed to support customers. This helps increase the chances of first time silicon success, which is critical in reducing time to market and overall costs at technologies of 90nm and below. Improved DFM solutions help customers realize enhanced yields, faster turnaround times, and reduced risk...
Synopsys’ Star-RCXT™ is the electronic design automation (EDA) industry’s gold standard forparasitic extraction. It provides a single solution for ASIC, system-on-chip (SoC), digital custom,memory and analog designs. Trusted by over 250 semiconductor companies and proven in thousandsof production designs, Star-RCXT delivers fast and sub-femtofarad accurate technology. The Star-RCXT solution offers advanced capabilities needed for sub-65-nanometer (nm) designs, includingvariation-aware parasitic extraction, chemical-mechanical polishing (CMP) based and litho-awareextraction, inductance extraction and analog mixed signal design flow. Its seamless integration withindustry leading physical verification, circuit simulation, timing, signal integrity, power, reliabilityand RTL2GDSII flows enables unmatched ease-of-use, increased productivity and reduced time-to-market. Star-RCXT is used by leading foundries to solve process modeling challenges at 65-nmand 45-nm.product:Synopsys Star-RCXT 2008.12 SP2 AMD64 Lanaguage:english Platform:Winxp/Win7 Size:138MB
Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time.product:Synopsys Formality 2008.09 SP4 Linux Lanaguage:english Platform:Winxp/Win7 Size:55MB
Crack Software Download