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The Synplify DSP tool provides a unique high-level synthesis methodology that realizes significant productivity and portability advantages. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations and results in significantly faster design capture, speeds time-to-market, and enables rapid design exploration for improved quality and lower cost.Product:Synopsys Synplify FPGA 2009.06 SP1 Linux Lanaguage:english Platform:Winxp/Win7 Size:516MB

RISA-2D is easy to learn, and powerful to use. With an intuitive interface and familiar spreadsheets, you can solve your next problem in minutes, not hours. Quickly analyze everything from simple beams and trusses to shear walls with openings. Break problems down to their basics and go. Packed with the most current steel, concrete, cold-formed steel, and timber design codes, RISA-2D gives you the tools to tackle multi-material projects with confidence. Advanced features such as flexible design rules and a custom concrete Layout Editor allow the engineer to control the design, not just the program. Product:RISA-2D 9.00 Lanaguage:english Platform:Winxp/Win7 Size:74MB

Cadence Assura 4.10 Linux Physical Verification supports both interactive and batch operation modes with a single set of design rules. It uses hierarchical processing and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification incorporates advanced sub-65nm process parameter measurement, nanometer design rules for DFM, and process design rule checks. Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® custom design environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration...

;Manusoft Technologies today unveiled IMOLD V9, the latest version with new and exciting user driven enhancements of its leading Computer-aided Mold Design (CAMD) software, IMOLD.IMOLD V9 aims to bridge the gaps between mold design and manufacturing through its new functions. With the new version releaseProduct:Imold 2009 v9 SP3 for Solidworks Win64 Lanaguage:english Platform:Winxp/Win7 Size:149MB

br />IMOLD V9 is not only SolidWorks 2009 ready but both 32 and 64 bit ready which, is yet another solid demonstration of Manusoft’s intent to ensure that it is ahead of competition. Beyond the label and specifications, IMOLD V9 is engineered to reduce design time of mold designers worldwide with its significant improvement in all round performance and help reduce carbon footprints by getting the molds right – before it is built. Product:IMOLD 2009 v9 SP3 FOR SOLIDWORKS Lanaguage:english Platform:Winxp/Win7 Size:146MB

FineSim Pro defines a new paradigm in full-chip circuit-level simulation, enabling the simulation of the most challenging analog/mixed-signal SoCs with SPICE accuracy and unprecedented performance. Combination of accuracy and performance in a single executable allows large, mixed-signal designs to be simulated with very accurate SPICE and fast-SPICE solving techniques. This provides complete control of speed- versus-accuracy tradeoffs throughout the entire design. Multi-CPU simulation enabled through Magma’s Native Parallel Technology TM delivers silicon-accurate results for very large complex systems (5M transistors and more) such as wireless systems on chip (SoCs) and full-chip memory designs. Electrically Exact Models TM (E2M) dramatically improve simulation performance by orders of magnitude with virtually no loss in accuracy compared to fast SPICE Typically, analog and digital...

ADS 2009 Update 1 is the 2nd of 4 quarterly releases in 2009 specifically targeted to double design productivity as measured in terms of reduction in simulation times, mouse clicks and activities needed to complete a design task. ADS 2009 Update 1 brings you the following exciting enhancements: 10x speedup in planar 3D electromagnetic simulation 10x speedup in non-linear circuit simulation Patent pending convolution technology that allows accurate signal integrity simulation with measured S-parameter data of high-speed interconnects New Simulation Models and Libraries Further improvement in graphical user interface The combined benefits of all the above translates to at least a doubling of your design productivity. 10x speedup in planar 3D electromagnetic simulation The 3D planar EM simulator, Momentum, in...

CoWare Processor Designer 2009.1 Programmable Accelerators for Platform-Driven ESL Design Integrated design environment for unified application specific processor, programmable accelerator design and software development tool generation Slashes application specific processor and programmable accelerator hardware design time by months Eliminates months of engineer-effort for software tool development Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation Software development environment enables application software development prior to silicon availability CoWare® Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time and engineer-month from the creation of application processor-specific software development tools. Processor Designer\’s high degree of automation enables design teams to focus on architecture exploration and application-specific processor development,...

Cadence  Incisive  Formal Verifier(IFV) allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages. Features/Benefits Speeds time to block design closure with early error detection, analysis, and debug Reduces risk of re-spin by finding bugs that other verification approaches miss Eases chip-level verification by delivering higher block-level verification quality Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies Supports all industry-standard assertion formats, including SystemVerilog Assertions (SVA),...

Agilent RF Design Environment (RFDE) provides access to the ADS circuit simulators directly from the Cadence Analog Design Environment (ADE). Note: RFDE is being replaced by Agilent\’s GoldenGate RFIC Design Software. RFDE 2009 is the last supported release. Agilent\’s GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE). ADS circuit simulators will continue to be accessible from ADE through the ADS Dynamic Link capability.Product:Agilent RF Design Environment (RFDE) 2008 Update2 Linux Lanaguage:english Platform:Winxp/Win7 Size:572MB