Tags :tutorial Page 78

Agilent VEE 8.5 New Features•Microsoft® Windows® Vista Support•Modern IDE with dockable tool windows•Newly designed Instrument Manager, Function & ObjectBrowser, and Output Window.•Color Coding•Dynamically change VISA Interface and Address•MATLAB® 2007a Support•Microsoft Office 2007 Support•Using Agilent IO monitor to monitor instant communi-cation•Uncertain data flow compiler warning•Exposing Main from callable server•Microsoft standard file open dialog•Per- user and per- version VEE configuration files•New data type – UInt16 and new execution mode – VEE8.5Product:Agilent VEE Pro 8.5 Lanaguage:english Platform:Winxp/Win7 Size:234MB

OverviewWith process geometries reaching90-nanometers (nm) and below, thereare many nanometer effects that canimpact timing. Accurate analysis ofthese effects is required to identify realtiming issues.Synopsys’ NanoTime tool is thenext-generation transistor-levelstatic timing analysis solution thataddresses the emerging challengesin signal integrity (SI) analysisassociated with custom designs.NanoTime offers concurrent timingand SI analysis, accuracy withinfive percent of HSPICE®, and theperformance required to analyzecomplex transistor circuits overnight.Its seamless integration with Synopsys’PrimeTime® product enables full-chipanalysis of designs that includes bothgate- and transistor-level blocks.NanoTime is a key component of theSynopsys custom design verificationsolution that includes CustomSim®and HSPICE for circuit simulationand ESP-CV for symbolic simulation.product:Synopsys Nanotime 2007.12 SP2 Linux Lanaguage:english Platform:Winxp/Win7 Size:81MB

IC-CAP 2008 (with Add-ons 1 & 2): Bringing Innovative Modeling Technology to Our Customers The IC-CAP 2008 release introduced the IC-CAP Target Modeling Package. Used to extract MOS models from semiconductor manufacturing process targets, the Target Modeling Package enables designers the to develop device simulation models earlier in the design cycle for faster overall integrated circuit design. The IC-CAP 2008 Add-On 1 release introduced the Hisim2.4 Model Extraction Package, an easy-to-use and efficient flow to measure and extract DC and RF parameters of the Hisim2.4.1 model. The IC-CAP 2008 Add-On 2 release introduced a similar extraction package for the Hisim_HV model for symmetrical HVMOS and asymmetrical LDMOS devices. New with this Release * Target Modeling Package * HiSIM2.4 Model Extraction...

attice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite Tool Suite Includes New 3rd Party Synthesis and Simulator Versions, Integrated ORCAstra Utility and Concurrent LatticeMico32 Release HILLSBORO, OR – SEPTEMBER 8, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Service Pack 1 for Version 7.1 of its ispLEVER® FPGA Design Tool Suite. The release integrates Lattice\’s ORCAstra configuration design utility, features Reveal™ Logic Analyzer support on the Linux Operating System, adds new versions of Synopsys\’ Synplify® Pro synthesis and Aldec\’s Active-HDL™ Lattice Edition simulator, includes support for automotive temperature grade LatticeXP2™ FPGAs and provides the latest LatticeMico32™ embedded open source microprocessor enhancements. \”This ispLEVER service pack adds a wide range of new utilities...

FPGA Advantage is a complete Integrated Design Environment (IDE) targeting high-complexity FPGA device design. The FPGA Advantage IDE spans the RTL FPGA design flow featuring advanced design entry, verification, synthesis and implementation sub-flows. FPGA Advantage accelerates total product design with integration of FPGA IO design as well as bi-directional integration of the PCB design flow. FPGA Advantage provides an integrated HDL flow for designing your FPGAs. FPGA Advantage enables design creation, simulation with debug and analysis, synthesis, management and documentation as a smooth flowing operation from one step to the next. Each component of FPGA Advantage is a proven point tool, but the power comes from integrating these tools tightly together to create a unique HDL design methodology environment for...

Incisive Desktop Manager  Automated verification management Incisive Desktop Manager automates and guides the everyday deployment and visualization of verification tasks and results, increasing engineering productivity and reducing time to market.Cadence® Incisive® Desktop Manager accelerates verification plan execution by automating time-consuming manual tasks at block, chip, system, and project levels. It manages the everyday deployment of common verification tasks, together with visualization of the results. Incisive Desktop Manager also supports a coverage-based verification and debug methodology that increases coverage using incrementally-developed verification plans. Features/Benefits Speeds time to results by automating verification tasks Increases engineering productivity by managing regression tests and failures Enables visualization of coverage results product:Cadence Incisive Desktop Manager (EMGR20) 2.0 Linux Lanaguage:english Platform:Winxp/Win7 Size:397MB

MoldWorks 2008 SP1 includes RTI catalogue and support for Vista Product:MoldWorks2008 SP1.0 for SolidWorks Win32 Lanaguage:english Platform:Winxp/Win7 Size:134MB

Cadence FINALE 6.1 Linuxproduct:Cadence FINALE 6.1 Linux Lanaguage:english Platform:Winxp/Win7 Size:544MB

ICEM Surf provides breakthrough technology enabling users to produce world-class aesthetic products in today\’s competitive, global markets. Acknowledged as the premier system for the creation and development of Class A surfaces, ICEM Surf bridges the demands of aesthetic designers and production engineers from visualisation right up to tool and die designers. The flexibility of ICEM Surf results in high-quality surfaces required in today\’s design environment, while substantially reducing overall design time. Product development teams using ICEM Surf leave the traditional process behind. ICEM Surf\’s integrated solutions enable users to implement a new, more efficient method of product development called Virtual Modelling. Stylists and engineers work out design treatments dynamically on screen and immediately see the aesthetic, as well as the...

Analog/mixed-signal extractor; provides high-speed parasitic extraction on full-chip layouts with silicon accuracy; part of the silicon analysis function inside the Virtuoso® custom design platformproduct:Cadence Assura 3.17-5141 Linux Lanaguage:english Platform:Winxp/Win7 Size:1.43G